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High Performance 8-Bit Microcontrollers
Z8 Encore!(R) 64K Series
Product Specification
PS019915-1005
ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126-3432 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters
532 Race Street San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. (c)2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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Revision History
Each instance in Table 1 reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table.
Table 1. Revision History of this Document Revision Level 12 13
Date January 2005 March 2005 August 2005
Description Added Die Form Sales information to Table 1. Provided timing equation when the Baud Rate Generator for a peripheral is used as a simple timer. Closes CR#5618.
Page # 2 109, 115, 131, 137, 155
14
Updated "Manual Objectives" on page xviii, "Introduction" on page 1, "Available Packages" on page 6, "Program Memory" on page 18, "Flash Memory" on page 178, "Option Bits" on page 190, "On-Chip Debugger Commands" on page 198, "Absolute Maximum Ratings" on page 209, "DC Characteristics" on page 211, Figure 48 on page 218, "On-Chip Peripheral AC and DC Electrical Characteristics" on page 219, "AC Characteristics" on page 224, "Ordering Information" on page 262, and "Part Number Suffix Designations" on page 267. Removed "Preliminary" from all pages. Deleted first sentence of "Electrical Characteristics" chapter. Deleted "Precharacterization Product" section in the "Packaging" chapter. Added automotive/industrial parts; removed all ROM references. The paragraph tag for "Ordering Information" has been changed from H1 Heading to Chapter Title. 262
October 2005
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv Manual Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset and STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watch-Dog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode Recovery Using Watch-Dog Timer Time-Out . . . . . . . . . . . . . . . . . . STOP Mode Recovery Using a GPIO Port Pin Transition HALT . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-H Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-H Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-H Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A-H Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19 19 21 26 43 43 43 44 44 45 46 46 47 47 48 48 49 49 49 50 51 51 51 52 52 54 54 55 56 60 61 62 62 62 64 64 64 65 65 65
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Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Interrupt Port Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Timer 0-3 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Timer 0-3 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Timer 0-3 Control 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Timer 0-3 Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Watch-Dog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Watch-Dog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Watch-Dog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Watch-Dog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Watch-Dog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Watch-Dog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . . . . 95 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . 101 Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . . . 103
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Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MULTIPROCESSOR (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
104 104 105 106 108 109 109 110 110 112 112 115 115 120 120 120 121 121 122 124 125 125 125 126 127 128 130 130 131 131 132 133 133 133 135 136 137 138 139 139 140
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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Write and Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Only Transaction with a 7-bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Only Transaction with a 10-bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . Write Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Diagnostic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA0 and DMA1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring DMA0 and DMA1 for Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . DMA_ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring DMA_ADC for Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMAx Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMAx I/O Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMAx Address High Nibble Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMAx Start/Current Address Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . DMAx End Address Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA_ADC Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA_ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140 141 141 142 143 143 144 145 146 147 149 150 152 152 153 155 156 158 160 161 161 161 161 162 162 163 163 163 165 165 166 166 167 168 169 171 171 171 172 172 173
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Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Control of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
173 174 175 175 176 176 178 178 180 180 181 181 181 182 183 184 184 184 185 185 186 187 188 189 190 190 190 190 190 191 192 193 193 193 194 194 195 196 196 197 197
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On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . . . . General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
198 202 202 204 205 205 205 205 207 209 209 211 219 224 225 226 227 228 229 230 231 233 233 234 234 237 238 242 252
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 267 268 269
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Z8 Encore!(R) 64K Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 64K Series in 40-Pin Dual Inline Package (PDIP) . . . . . . . . . . . . . . . . . . . . 7 64K Series in 44-Pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . . 8 64K Series in 44-Pin Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . 9 64K Series in 64-Pin Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . 10 64K Series in 68-Pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . 11 64K Series in 80-Pin Quad Flat Package (QFP) . . . . . . . . . . . . . . . . . . . . . 12 Power-On Reset Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . 100 UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . 100 UART Asynchronous MULTIPROCESSOR Mode Data Format . . . . . . 104 UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . 108 Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . . 120 Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 SPI Configured as a Master in a Single Master, Single Slave System . . . 125 SPI Configured as a Master in a Single Master, Multiple Slave System . . 126 SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SPI Timing When PHASE is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SPI Timing When PHASE is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7-Bit Address Only Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . 145 10-Bit Address Only Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . 146 10-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . 147 Receive Data Transfer Format for a 7-Bit Addressed Slave . . . . . . . . . . . 149
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Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64.
Receive Data Format for a 10-Bit Addressed Slave . . . . . . . . . . . . . . . . . Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Data Format 196 Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45kW Resistor . . . . . . . . . . . . . . . . . . . . . . . Typical Active Mode Idd Versus System Clock Frequency . . . . . . . . . . . Maximum Active Mode Idd Versus System Clock Frequency . . . . . . . . . Typical HALT Mode Idd Versus System Clock Frequency . . . . . . . . . . . Maximum HALT Mode Icc Versus System Clock Frequency . . . . . . . . . Maximum STOP Mode Idd with VBO enabled versus Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum STOP Mode Idd with VBO Disabled versus Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter Frequency Response . . . . . . . . . . . . . . . . . . Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Second Opcode Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-Lead Plastic Dual-Inline Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . 44-Lead Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . . . . . . . . . 44-Lead Plastic Lead Chip Carrier Package (PLCC) . . . . . . . . . . . . . . . .
150 172 179 193 194 195 206 207 208 213 214 215 216 217 218 223 225 226 227 228 229 230 231 232 252 253 255 256 257 258 259
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Figure 65. 64-Lead Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . . . . . . . . . 259 Figure 66. 68-Lead Plastic Lead Chip Carrier Package (PLCC) . . . . . . . . . . . . . . . . 260 Figure 67. 80-Lead Quad-Flat Package (QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
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List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Revision History of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii Z8 Encore!(R) 64K Series Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . 2 Z8 Encore!(R) 64K Series Package Options . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Characteristics of the 64K Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Z8 Encore(R) 64K Series Program Memory Maps . . . . . . . . . . . . . . . . . . . . 18 Z8 Encore!(R) 64K Series Information Area Map . . . . . . . . . . . . . . . . . . . . 20 64K Series Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset and STOP Mode Recovery Characteristics and Latency . . . . . . . . . . 43 Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STOP Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . 47 Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 51 Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Port A-H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . . 55 GPIO Port Registers and Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Port A-H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Port A-H Data Direction Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Port A-H Alternate Function Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . 57 Port A-H Output Control Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Port A-H High Drive Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . 59 Port A-H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Port A-H STOP Mode Recovery Source Enable Sub-Registers . . . . . . . . . 60 Port A-H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 69 IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 70 IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 71 IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69.
IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 71 IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . . 72 IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . 72 Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Interrupt Port Select Register (IRQPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Timer 0-3 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Timer 0-3 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Timer 0-3 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . 86 Timer 0-3 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . . 86 Timer 0-3 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . . . 87 Timer 0-3 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . . . 87 Timer 0-3 Control 0 Register (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Timer 0-3 Control 1 Register (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . 92 Watch-Dog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . 94 Watch-Dog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . 96 Watch-Dog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . 96 Watch-Dog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . 97 UART Transmit Data Register (UxTXD) . . . . . . . . . . . . . . . . . . . . . . . . . 109 UART Receive Data Register (UxRXD) . . . . . . . . . . . . . . . . . . . . . . . . . . 110 UART Status 0 Register (UxSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 UART Status 1 Register (UxSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UART Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 UART Control 1 Register (UxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 UART Address Compare Register (UxADDR) . . . . . . . . . . . . . . . . . . . . . 115 UART Baud Rate High Byte Register (UxBRH) . . . . . . . . . . . . . . . . . . . 116 UART Baud Rate Low Byte Register (UxBRL) . . . . . . . . . . . . . . . . . . . . 116 UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation . . . 128 SPI Data Register (SPIDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 SPI Diagnostic State Register (SPIDST) . . . . . . . . . . . . . . . . . . . . . . . . . . 137 SPI Baud Rate High Byte Register (SPIBRH) . . . . . . . . . . . . . . . . . . . . . 138
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xvi
Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105.
SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . . . . . . . . . . . . . . I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Status Register (I2CSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . . I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . . I2C Diagnostic State Register (I2CDST) . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Diagnostic Control Register (I2CDIAG) . . . . . . . . . . . . . . . . . . . . . . DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . . . . . . . . . . . . . . DMAx Address High Nibble Register (DMAxH) . . . . . . . . . . . . . . . . . . . DMAx Start/Current Address Low Byte Register (DMAxSTART) . . . . . DMAx End Address Low Byte Register (DMAxEND) . . . . . . . . . . . . . . DMA_ADC Register File Address Example . . . . . . . . . . . . . . . . . . . . . . . DMA_ADC Address Register (DMAA_ADDR) . . . . . . . . . . . . . . . . . . . DMA_ADC Control Register (DMAACTL) . . . . . . . . . . . . . . . . . . . . . . . DMA_ADC Status Register (DMAA_STAT) . . . . . . . . . . . . . . . . . . . . . . ADC Control Register (ADCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64K Series Information Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . Flash Option Bits At Flash Memory Address 0000H . . . . . . . . . . . . . . . . Options Bits at Flash Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Crystal Oscillator Specifications (20MHz Operation) . . .
138 153 153 155 157 157 158 160 164 165 165 166 167 167 168 169 170 175 176 177 178 179 180 185 186 187 188 189 189 191 192 196 198 203 204 206
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Table 106. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 107. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 108. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 109. Reset and STOP Mode Recovery Pin Timing . . . . . . . . . . . . . . . . . . . . . . Table 110. External RC Oscillator Electrical Characteristics and Timing . . . . . . . . . Table 111. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . Table 112. Watch-Dog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . Table 113. Analog-to-Digital Converter Electrical Characteristics and Timing . . . . . Table 114. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 115. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 116. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 117. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 118. SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 119. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 120. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 121. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 122. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 123. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 124. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 125. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 126. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 127. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 128. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 129. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 130. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 131. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 132. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 133. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 134. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 135. Opcode Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
209 211 219 220 220 221 221 222 224 225 226 227 228 229 230 231 232 235 236 237 238 239 239 240 240 241 241 242 242 254
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Manual Objectives
This Product Specification provides detailed operating information for the Flash devices within the Z8 Encore!(R) 64K Series Microcontroller (MCU) products. Within this document, the Z8F642x, Z8F482x, Z8F322x, Z8F242x, and Z8F162x devices are referred to collectively as the Z8 Encore!(R) 64K Series unless specifically stated otherwise.
About This Manual
ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product. However, we recognize that there are different styles of learning. Therefore, we have designed this Product Specification to be used either as a how to procedural manual or a reference guide to important data.
Intended Audience
This document is written for ZiLOG customers who are experienced at working with microcontrollers, integrated circuits, or printed circuit assemblies.
Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use: Courier Typeface Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the Courier typeface. Where the use of the font is not indicated, as in the Index, the name of the entity is presented in upper case.
*
Example: FLAGS[1] is smrf.
Hexadecimal Values Hexadecimal values are designated by uppercase H suffix and appear in the Courier typeface.
*
Example: R1 is set to F8H.
Brackets The square brackets, [ ], indicate a register or bus.
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*
Example: for the register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant bit, and R1[0] is the least significant bit.
Braces The curly braces, { }, indicate a single register or bus created by concatenating some combination of smaller registers, buses, or individual bits.
*
Example: the 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer (RP) and Working Register R1. 0H is the most significant nibble (4-bit value) of the 12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.
Parentheses The parentheses, ( ), indicate an indirect register address lookup.
*
Example: (R1) is the memory location referenced by the address contained in the Working Register R1.
Parentheses/Bracket Combinations The parentheses, ( ), indicate an indirect register address lookup and the square brackets, [ ], indicate a register or bus.
*
Example: assume PC[15:0] contains the value 1234h. (PC[15:0]) then refers to the contents of the memory location at address 1234h.
Use of the Words Set, Reset and Clear The word set implies that a register bit or a condition contains a logical 1. The words reset or clear imply that a register bit or a condition contains a logical 0. When either of these terms is followed by a number, the word logical may not be included; however, it is implied. Notation for Bits and Similar Registers A field of bits within a register is designated as: Register[n:n].
*
Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address.
Use of the Terms LSB, MSB, lsb, and msb In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms, lsb and msb, mean least significant bit and most significant bit, respectively. Use of Initial Uppercase Letters Initial uppercase letters designate settings and conditions in general text.
*
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Example 1: The receiver forces the SCL line to Low.
Manual Objectives
Z8 Encore!(R) 64K Series Product Specification
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*
Example 2: The Master can generate a Stop condition to abort the transfer.
Use of All Uppercase Letters The use of all uppercase letters designates the names of states, modes, and commands.
* * *
Example 1: The bus is considered BUSY after the Start condition. Example 2: A START command triggers the processing of the initialization sequence. Example 3: STOP mode
Bit Numbering Bits are numbered from 0 to n-1 where n indicates the total number of bits. For example, the 8 bits of a register are numbered from 0 to 7.
Safeguards
It is important that all users understand the following safety terms, which are defined here. Caution: Indicates a procedure or file may become corrupted if the user does not follow directions.
Trademarks
ZiLOG(R), eZ8, Z8 Encore!(R), and Z8(R) are trademarks of ZiLOG, Inc. in the U.S.A. and other countries. All other trademarks are the property of their respective corporations.
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Z8 Encore!(R) 64K Series Product Specification
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Introduction
The Z8 Encore!(R) MCU family of products are a line of ZiLOG microcontroller products based upon the 8-bit eZ8 CPU. The Z8 Encore!(R) 64K Series, hereafter referred to collectively as the Z8 Encore!(R) or the 64K Series adds Flash memory to ZiLOG's extensive line of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster development time and program changes in the field. The new eZ8 CPU is upward compatible with existing Z8(R) instructions. The rich peripheral set of the Z8 Encore!(R) makes it suitable for a variety of applications including motor control, security systems, home appliances, personal electronic devices, and sensors.
Features * * * * * * * * * * * * * * * *
20 MHz eZ8 CPU Up to 64 KB Flash with in-circuit programming capability Up to 4 KB register RAM 12-channel, 10-bit analog-to-digital converter (ADC) Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control I2C Serial Peripheral Interface Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders Up to four 16-bit timers with capture, compare, and PWM capability Watch-Dog Timer (WDT) with internal RC oscillator 3-channel DMA Up to 60 I/O pins 24 interrupts with configurable priority On-Chip Debugger Voltage Brown-out Protection (VBO) Power-On Reset (POR)
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* *
3.0-3.6V operating voltage with 5V-tolerant inputs 0 to +70C, -40 to +105C, and -40 to +125C operating temperature ranges
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the Z8 Encore!(R) product line.
Table 1. Z8 Encore!(R) 64K Series Part Selection Guide Part Number Z8F1621 Z8F1622 Z8F2421 Z8F2422 Z8F3221 Z8F3222 Z8F4821 Z8F4822 Z8F4823 Z8F6421 Z8F6422 Z8F6423 Die Form Sales Flash (KB) 16 16 24 24 32 32 48 48 48 64 64 64 Please contact ZiLOG RAM 16-bit Timers ADC UARTs 40/44-pin 64/68-pin 80-pin (KB) I/O with PWM Inputs with IrDA I2C SPI packages packages package 2 2 2 2 2 2 4 4 4 4 4 4 31 46 31 46 31 46 31 46 60 31 46 60 3 4 3 4 3 4 3 4 4 3 4 4 8 12 8 12 8 12 8 12 12 8 12 12 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X
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Z8 Encore!(R) 64K Series Product Specification
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Block Diagram
Figure 1 illustrates the block diagram of the architecture of the Z8 Encore!(R) 64K Series.
XTAL / RC Oscillator
On-Chip Debugger POR/VBO & Reset Controller
eZ8 CPU System Clock
Interrupt Controller
WDT with RC Oscillator
Memory Busses Register Bus
Timers
UARTs
I2C
SPI
ADC
DMA
Flash Controller
RAM Controller
IrDA
Flash Memory
RAM
GPIO
Figure 1. Z8 Encore!(R) 64K Series Block Diagram
CPU and Peripheral Overview
eZ8 CPU Features
The eZ8, ZiLOG's latest 8-bit Central Processing Unit (CPU), meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The eZ8 CPU features include:
*
Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory
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Z8 Encore!(R) 64K Series Product Specification
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* * * * * * * * * *
Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks Compatible with existing Z8(R) code Expanded internal Register File allows access of up to 4KB New instructions improve execution efficiency for code developed using higher-level programming languages, including C Pipelined instruction fetch and execution New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC, LDCI, LEA, MULT, and SRL New instructions support 12-bit linear addressing of the Register File Up to 10 MIPS operation C-Compiler friendly 2-9 clock cycles per instruction
For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual available for download at www.zilog.com.
General Purpose I/O
The 64K Series features seven 8-bit ports (Ports A-G) and one 4-bit port (Port H) for general purpose I/O (GPIO). Each pin is individually programmable. All ports (except B and H) support 5V-tolerant inputs.
Flash Controller
The Flash Controller programs and erases the Flash memory.
10-Bit Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary number. The ADC accepts inputs from up to 12 different analog input sources.
UARTs
Each UART is full-duplex and capable of handling asynchronous data transfers. The UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver Driver Enable signal for controlling a multi-transceiver bus, such as RS-485.
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I2C
The inter-integrated circuit (I2C(R)) controller makes the Z8 Encore!(R) compatible with the I2C protocol. The I2C controller consists of two bidirectional bus lines, a serial data (SDA) line and a serial clock (SCL) line.
Serial Peripheral Interface
The serial peripheral interface (SPI) allows the Z8 Encore!(R) to exchange data between other peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface.
Timers
Up to four 16-bit reloadable timers can be used for timing/counting events or for motor control operations. These timers provide a 16-bit programmable reload counter and operate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM modes. Only 3 timers (Timers 0-2) are available in the 44-pin packages.
Interrupt Controller
The 64K Series products support up to 24 interrupts. These interrupts consist of 12 internal and 12 general-purpose I/O pins. The interrupts have 3 levels of programmable interrupt priority.
Reset Controller
The Z8 Encore!(R) can be reset using the RESET pin, power-on reset, Watch-Dog Timer (WDT), STOP mode exit, or Voltage Brown-Out (VBO) warning signal.
On-Chip Debugger
The Z8 Encore!(R) features an integrated On-Chip Debugger (OCD). The OCD provides a rich set of debugging capabilities, such as reading and writing registers, programming the Flash, setting breakpoints and executing code. A single-pin interface provides communication to the OCD.
DMA Controller
The 64K Series features three channels of DMA. Two of the channels are for register RAM to and from I/O operations. The third channel automatically controls the transfer of data from the ADC to the memory.
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Z8 Encore!(R) 64K Series Product Specification
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Signal and Pin Descriptions
Overview
The Z8 Encore!(R) 64K Series products are available in a variety of packages styles and pin configurations. This chapter describes the signals and available pin configurations for each of the package styles. For information regarding the physical package specifications, please refer to Packaging on page 257.
Available Packages
Table 2 identifies the package styles that are available for each device within the Z8
Encore!(R) 64K Series product line. Table 2. Z8 Encore!(R) 64K Series Package Options 40-Pin PDIP X 44-pin LQFP X 44-pin PLCC X X X X X X X X X X X X X X X X X X X X X X X X X 64-pin LQFP 68-pin PLCC 80-pin QFP
Part Number Z8F1621 Z8F1622 Z8F2421 Z8F2422 Z8F3221 Z8F3222 Z8F4821 Z8F4822 Z8F4823 Z8F6421 Z8F6422 Z8F6423
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Z8 Encore!(R) 64K Series Product Specification
7
Pin Configurations
Figures 2 through 7 illustrate the pin configurations for all of the packages available in the 64K Series. Refer to Table 3 for a description of the signals. Timer 3 is not available in the 40-pin and 44-pin packages.
PD4/RXD1 PD3 / DE1 PC5 / MISO PA3 / CTS0 PA2/DE0 PA1 /T0OUT PA0 / T0IN PC2 / SS RESET VDD VSS PD1 PD0 XOUT XIN AVDD PB0 / ANA0 PB1 / ANA1 PB4 / ANA4 PB5 / ANA5 Note: Timer 3 is not supported.
1
40
PD5 / TXD1 PC4 / MOSI PA4 / RXD0 PA5 / TXD0 PA6 / SCL
5 35
PA7 / SDA PD6 / CTS1 PC3 / SCK VSS VDD
10 30
PC6 / T2IN * DBG PC1 / T1OUT PC0 / T1IN
15 25
AVSS VREF PB2 / ANA2 PB3 / ANA3 PB7 / ANA7 PB6 / ANA6 * T2OUT is not supported.
20
21
Figure 2. 64K Series in 40-Pin Dual Inline Package (PDIP)
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Signal and Pin Descriptions
Z8 Encore!(R) 64K Series Product Specification
8
PA1 / T0OUT PA2 / DE0
PD3 / DE1 PD4 / RXD1 PD5 / TXD1 PC4 / MOSI
PA3 / CTS0 PC5 / MISO
PA4 / RXD0 PA5 / TXD0
6 PA0 / T0IN PD2 PC2 / SS RESET VDD VSS PD1 PD0 XOUT XIN VDD 17 18 AVDD PB0 / ANA0 PB1 / ANA1 PB4 / ANA4 PB5 / ANA5 12 7
1
40 39
PA6 / SCL PA7 / SDA PD6 / CTS1 PC3 / SCK VSS VDD 34 PC7 / T2OUT PC6 / T2IN DBG PC1 / T1OUT PC0 / T1IN 29 28 VSS
23 PB7 / ANA7 PB3 / ANA3 PB6 / ANA6
Figure 3. 64K Series in 44-Pin Plastic Leaded Chip Carrier (PLCC)
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PB2 / ANA2 VREF AVSS
Signal and Pin Descriptions
Z8 Encore!(R) 64K Series Product Specification
9
PA1 / T0OUT PA2 / DE0
PD3 / DE1 PD4 / RXD1 PD5 / TXD1 PC4 / MOSI
PA3 / CTS0 PC5 / MISO
PA4 / RXD0 PA5 / TXD0
PA0 / T0IN PD2 PC2 / SS RESET VDD VSS PD1 PD0 XOUT XIN VDD
33 34
28
23 22
PA6 / SCL PA7 / SDA PD6 / CTS1 PC3 / SCK VSS 17 VDD PC7 / T2OUT PC6 / T2IN DBG PC1 / T1OUT PC0 / T1IN VSS 12 11
39
44
1 PB4 / ANA4 PB5 / ANA5
6 PB6 / ANA6 PB7 / ANA7 PB3 / ANA3
AVDD PB0 / ANA0 PB1 / ANA1
Figure 4. 64K Series in 44-Pin Low-Profile Quad Flat Package (LQFP)
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PB2 / ANA2 VREF AVSS
Signal and Pin Descriptions
Z8 Encore!(R) 64K Series Product Specification
10
PA1 / T0OUT PA2 / DE0
PD4 / RXD1 PD5 / TXD1
VDD PF7 PC5 / MISO PD3 / DE1
PA0 / T0IN PD2 PC2 / SS RESET VDD PE4 PE3 VSS PE2 PE1 PE0 VSS PD1 / T3OUT PD0 / T3IN XOUT XIN
48 49
40
PA4 / RXD0 PA5 / TXD0 PA6 / SCL 33 32 PA7 / SDA PD6 / CTS1 PC3 / SCK PD7 / RCOUT VSS PE5 PE6 25 PE7 VDD PG3 VDD PC7 / T2OUT PC6 / T2IN DBG PC1 / T1OUT PC0 / T1IN 17 16 PH3 / ANA11 VREF AVSS
PC4 / MOSI
PA3 / CTS0 VSS
56
64
1 PH1 / ANA9 PB0 / ANA0 PB1 / ANA1
8 PB6 / ANA6 PB7 / ANA7 PB3 / ANA3 PB2 / ANA2 PH2 / ANA10 PB4 / ANA4 PB5 / ANA5
Figure 5. 64K Series in 64-Pin Low-Profile Quad Flat Package (LQFP)
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VSS AVDD PH0 / ANA8
VDD VSS
Signal and Pin Descriptions
Z8 Encore!(R) 64K Series Product Specification
11
PA1 / T0OUT PA2 / DE0
PD4 / RXD1 PD5 / TXD1
VDD PF7 PC5 / MISO PD3 / DE1
9 PA0 / T0IN PD2 PC2 / SS RESET VDD PE4 PE3 VSS PE2 PE1 PE0 VSS VDD PD1 / T3OUT PD0 / T3IN XOUT XIN 18 10
1
VSS PA4 / RXD0 PA5 / TXD0 PA6 / SCL 61 60 PA7 / SDA PD6 / CTS1 PC3 / SCK PD7 / RCOUT VSS PE5 PE6 PE7 52 VDD PG3 VDD PC7 / T2OUT PC6 / T2IN DBG PC1 / T1OUT PC0 / T1IN VSS 44 43 PH3 / ANA11 VREF AVSS AVSS
PC4 / MOSI VDD
PA3 / CTS0 VSS
26 27 AVDD PH0 / ANA8 PH1 / ANA9 PB0 / ANA0 PB1 / ANA1 PB4 / ANA4 PB5 / ANA5 VSS
35 PB6 / ANA6 PB7 / ANA7 PB3 / ANA3 PB2 / ANA2 PH2 / ANA10
Figure 6. 64K Series in 68-Pin Plastic Leaded Chip Carrier (PLCC)
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VDD
Signal and Pin Descriptions
Z8 Encore!(R) 64K Series Product Specification
12
PA1 / T0OUT PA2 / DE0
PD4 / RXD1 PD5 / TXD1
VDD PF7 PC5 / MISO PD3 / DE1
PA0 / T0IN PD2 PC2 / SS PF6 RESET VDD PF5 PF4 PF3 PE4 PE3 VSS PE2 PE1 PE0 VSS PF2 PF1 PF0 VDD PD1 / T3OUT PD0 / T3IN XOUT XIN
1
80
75
70
PA4 / RXD0 PA5 / TXD0 PA6 / SCL 65 64
PC4 / MOSI
PA3 / CTS0 VSS
VDD VSS
PA7 / SDA PD6 / CTS1 PC3 / SCK PD7 / RCOUT
5
60
PG0 VSS PG1 PG2 PE5
10
55
PE6 PE7 VDD PG3 PG4
15
50
PG5 PG6 VDD PG7 PC7 / T2OUT PC6 / T2IN DBG PC1 / T1OUT PC0 / T1IN
20
45
24 25 AVDD PH0 / ANA8 VSS PH1 / ANA9 PB0 / ANA0
30 PB1 / ANA1 PB4 / ANA4 PB5 / ANA5 PB6 / ANA6 PB7 / ANA7
35 PB3 / ANA3 PB2 / ANA2 PH2 / ANA10
41 40 PH3 / ANA11 VREF AVSS
VSS
Figure 7. 64K Series in 80-Pin Quad Flat Package (QFP)
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Signal Descriptions
Table 3 describes the Z8 Encore! signals. Refer to the section Pin Configurations on page 7 to determine the signals available for the specific package styles.
Table 3. Signal Descriptions Signal Mnemonic
I/O
Description
General-Purpose I/O Ports A-H PA[7:0] PB[7:0] PC[7:0] PD[7:0] PE[7:0] PF[7:0] PG[7:0] PH[3:0] I2C Controller SCL O Serial Clock. This is the output clock for the I2C. This pin is multiplexed with a general-purpose I/O pin. When the general-purpose I/O pin is configured for alternate function to enable the SCL function, this pin is open-drain. Serial Data. This open-drain pin transfers data between the I2C and a slave. This pin is multiplexed with a general-purpose I/O pin. When the general-purpose I/O pin is configured for alternate function to enable the SDA function, this pin is open-drain. I/O I/O I/O I/O I/O I/O I/O I/O Port A[7:0]. These pins are used for general-purpose I/O and support 5V-tolerant inputs. Port B[7:0]. These pins are used for general-purpose I/O. Port C[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs Port D[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs Port E[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs. Port F[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs. Port G[7:0]. These pins are used for general-purpose I/O. These pins are used for general-purpose I/O and support 5V-tolerant inputs. Port H[3:0]. These pins are used for general-purpose I/O.
SDA
I/O
SPI Controller
SS
I/O
Slave Select. This signal can be an output or an input. If the Z8 Encore!(R) 64K Series is the SPI master, this pin may be configured as the Slave Select output. If the Z8 Encore!(R) 64K Series is the SPI slave, this pin is the input slave select. It is multiplexed with a general-purpose I/O pin. SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore! 64K(R) Series is the SPI master, this pin is an output. If the Z8 Encore!(R) 64K Series is the SPI slave, this pin is an input. It is multiplexed with a general-purpose I/O pin.
SCK
I/O
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Table 3. Signal Descriptions (Continued) Signal Mnemonic MOSI
I/O I/O
Description Master Out Slave In. This signal is the data output from the SPI master device and the data input to the SPI slave device. It is multiplexed with a general-purpose I/O pin. Master In Slave Out. This pin is the data input to the SPI master device and the data output from the SPI slave device. It is multiplexed with a general-purpose I/O pin.
MISO UART Controllers TXD0 / TXD1 RXD0 / RXD1
I/O
O I I O
Transmit Data. These signals are the transmit outputs from the UARTs. The TXD signals are multiplexed with general-purpose I/O pins. Receive Data. These signals are the receiver inputs for the UARTs and IrDAs. The RXD signals are multiplexed with general-purpose I/O pins. Clear To Send. These signals are control inputs for the UARTs. The CTS signals are multiplexed with general-purpose I/O pins. Driver Enable. This signal allows automatic control of external RS-485 drivers. This signal is approximately the inverse of the TXE (Transmit Empty) bit in the UART Status 0 register. The DE signal may be used to ensure an external RS-485 driver is enabled when data is transmitted by the UART.
CTS0 / CTS1 DE0 / DE1
Timers T0OUT / T1OUT/ T2OUT / T3OUT T0IN / T1IN/ T2IN / T3IN Analog ANA[11:0] VREF I I Analog Input. These signals are inputs to the analog-to-digital converter (ADC). The ADC analog inputs are multiplexed with general-purpose I/O pins. Analog-to-digital converter reference voltage input. The VREF pin must be left unconnected (or capacitively coupled to analog ground) if the internal voltage reference is selected as the ADC reference voltage. O Timer Output 0-3. These signals are output pins from the timers. The Timer Output signals are multiplexed with general-purpose I/O pins. T3OUT is not available in 44pin package devices. Timer Input 0-3. These signals are used as the capture, gating and counter inputs. The Timer Input signals are multiplexed with general-purpose I/O pins. T3IN is not available in 44-pin package devices.
I
Oscillators XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal can be connected between it and the XOUT pin to form the oscillator. This signal is usable with external RC networks and an external clock driver.
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Table 3. Signal Descriptions (Continued) Signal Mnemonic XOUT
I/O O
Description External Crystal Output. This pin is the output of the crystal oscillator. A crystal can be connected between it and the XIN pin to form the oscillator. When the system clock is referred to in this manual, it refers to the frequency of the signal at this pin. This pin must be left unconnected when not using a crystal. RC Oscillator Output. This signal is the output of the RC oscillator. It is multiplexed with a general-purpose I/O pin. This signal must be left unconnected when not using a crystal.
RCOUT
O
On-Chip Debugger DBG Debug. This pin is the control and data input and output to and from the On-Chip Debugger. This pin is open-drain. Caution:For operation of the On-Chip Debugger, all power pins (VDD and AVDD) must be supplied with power and all ground pins (VSS and AVSS) must be properly grounded. The DBG pin is open-drain and must have an external pull-up resistor to ensure proper operation. I/O
Reset
RESET
Power Supply VDD AVDD VSS AVSS
I
RESET. Generates a Reset when asserted (driven Low).
I I I I
Power Supply. Analog Power Supply. Ground. Analog Ground.
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Pin Characteristics
Table 4 provides detailed information on the characteristics for each pin available on the 64K Series products. Data in Table 4 is sorted alphabetically by the pin symbol mnemonic.
Table 4. Pin Characteristics of the 64K Series Active Low or Active High N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Low N/A N/A N/A Internal Pull-up or Pull-down No No No No No No No No No No No No Pull-up No No No Schmitt Trigger Input No No Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No
Symbol Mnemonic AVSS AVDD DBG VSS PA[7:0] PB[7:0] PC[7:0] PD[7:0] PE7:0] PF[7:0] PG[7:0] PH[3:0] RESET VDD XIN XOUT
Direction N/A N/A I/O N/A I/O I/O I/O I/O I/O I/O I/O I/O I N/A I O
Reset Direction N/A N/A I N/A I I I I I I I I I N/A I O
Tri-State Output N/A N/A Yes N/A Yes Yes Yes Yes Yes Yes Yes Yes N/A N/A N/A Yes, in STOP mode
Open Drain Output N/A N/A Yes N/A Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable Yes, Programmable N/A N/A N/A No
x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer
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Address Space
Overview
The eZ8 CPU can access three distinct address spaces:
* * *
The Register File contains addresses for the general-purpose registers and the eZ8 CPU, peripheral, and general-purpose I/O port control registers. The Program Memory contains addresses for all memory locations having executable code and/or data. The Data Memory contains addresses for all memory locations that hold data only.
These three address spaces are covered briefly in the following subsections. For more detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU User Manual available for download at www.zilog.com.
Register File
The Register File address space in the 64K Series is 4KB (4096 bytes). The Register File is composed of two sections--control registers and general-purpose registers. When instructions are executed, registers are read from when defined as sources and written to when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. The upper 256 bytes of the 4KB Register File address space are reserved for control of the eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at addresses from F00H to FFFH. Some of the addresses within the 256-byte control register section are reserved (unavailable). Reading from an reserved Register File addresses returns an undefined value. Writing to reserved Register File addresses is not recommended and can produce unpredictable results. The on-chip RAM always begins at address 000H in the Register File address space. The 64K Series provide 2KB to 4KB of on-chip RAM depending upon the device. Reading from Register File addresses outside the available RAM addresses (and not within the control register address space) returns an undefined value. Writing to these Register File addresses produces no effect. Refer to the Part Selection Guide on page 2 to determine the amount of RAM available for the specific 64K Series device.
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Program Memory
The eZ8 CPU supports 64 KB of Program Memory address space. The Z8 Encore!(R) 64K Series contains 16 KB to 64 KB of on-chip Flash in the Program Memory address space, depending upon the device. Reading from Program Memory addresses outside the available Flash memory addresses returns FFH. Writing to these unimplemented Program Memory addresses produces no effect. Table 5 describes the Program Memory Maps for the 64K Series products.
Table 5. Z8 Encore(R) 64K Series Program Memory Maps Program Memory Address (Hex) Z8F162x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-3FFF Z8F242x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-5FFF Z8F322x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-7FFF Option Bits Reset Vector WDT Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Option Bits Reset Vector WDT Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Option Bits Reset Vector WDT Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Function
* See Table 23 on page 63 for a list of the interrupt vectors.
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Table 5. Z8 Encore(R) 64K Series Program Memory Maps (Continued) Program Memory Address (Hex) Z8F482x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-BFFF Z8F642x Products 0000-0001 0002-0003 0004-0005 0006-0007 0008-0037 0038-FFFF Option Bits Reset Vector WDT Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Option Bits Reset Vector WDT Interrupt Vector Illegal Instruction Trap Interrupt Vectors* Program Memory Function
* See Table 23 on page 63 for a list of the interrupt vectors.
Data Memory
The Z8 Encore!(R) 64K Series does not use the eZ8 CPU's 64KB Data Memory address space.
Information Area
Table 6 describes the Z8 Encore!(R) 64K Series Information Area. This 512 byte Information Area is accessed by setting bit 7 of the Page Select Register to 1. When access is enabled, the Information Area is mapped into the Program Memory and overlays the 512 bytes at addresses FE00H to FFFFH. When the Information Area access is enabled, execution of LDC and LDCI instruction from these Program Memory addresses return the Information Area data rather than the Program Memory data. Reads of these addresses through the On-Chip Debugger also returns the Information Area data. Execution of code from these addresses continues to correctly use the Program Memory. Access to the Information Area is read-only.
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Table 6. Z8 Encore!(R) 64K Series Information Area Map Program Memory Address (Hex) FE00H-FE3FH FE40H-FE53H Function Reserved Part Number 20-character ASCII alphanumeric code Left justified and filled with zeros (ASCII Null character). Reserved
FE54H-FFFFH
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Register File Address Map
Table 7 provides the address map for the Register File of the 64K Series products. Not all devices and package styles in the 64K Series support Timer 3 and all of the GPIO Ports. Consider registers for unimplemented peripherals as Reserved.
Table 7. 64K Series Register File Address Map Address (Hex) Register Description Mnemonic -- T0H T0L T0RH T0RL T0PWMH T0PWML T0CTL0 T0CTL1 T1H T1L T1RH T1RL T1PWMH T1PWML T1CTL0 T1CTL1 T2H T2L T2RH T2RL T2PWMH T2PWML T2CTL0 T2CTL1 Reset (Hex) XX 00 01 FF FF 00 00 00 00 00 01 FF FF 00 00 00 00 00 01 FF FF 00 00 00 00 84 84 85 85 87 87 88 88 84 84 85 85 87 87 88 88 84 84 85 85 87 87 88 88 Page # General Purpose RAM 000-EFF General-Purpose Register File RAM Timer 0 F00 F01 F02 F03 F04 F05 F06 F07 Timer 1 F08 F09 F0A F0B F0C F0D F0E F0F Timer 2 F10 F11 F12 F13 F14 F15 F16 F17 XX=Undefined Timer 0 High Byte Timer 0 Low Byte Timer 0 Reload High Byte Timer 0 Reload Low Byte Timer 0 PWM High Byte Timer 0 PWM Low Byte Timer 0 Control 0 Timer 0 Control 1 Timer 1 High Byte Timer 1 Low Byte Timer 1 Reload High Byte Timer 1 Reload Low Byte Timer 1 PWM High Byte Timer 1 PWM Low Byte Timer 1 Control 0 Timer 1 Control 1 Timer 2 High Byte Timer 2 Low Byte Timer 2 Reload High Byte Timer 2 Reload Low Byte Timer 2 PWM High Byte Timer 2 PWM Low Byte Timer 2 Control 0 Timer 2 Control 1
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Table 7. 64K Series Register File Address Map (Continued) Address (Hex) Register Description Mnemonic T3H T3L T3RH T3RL T3PWMH T3PWML T3CTL0 T3CTL1 -- U0TXD U0RXD U0STAT0 U0CTL0 U0CTL1 U0STAT1 U0ADDR U0BRH U0BRL U1TXD U1RXD U1STAT0 U1CTL0 U1CTL1 U1STAT1 U1ADDR U1BRH U1BRL I2CDATA I2CSTAT I2CCTL I2CBRH I2CBRL I2CDST I2CDIAG -- Reset (Hex) 00 01 FF FF 00 00 00 00 XX XX XX 0000011Xb 00 00 00 00 FF FF XX XX 0000011Xb 00 00 00 00 FF FF 00 80 00 FF FF C0 00 XX Page # 84 84 85 85 87 87 88 88 Timer 3 (unavailable in the 44-pin packages) F18 Timer 3 High Byte F19 Timer 3 Low Byte F1A Timer 3 Reload High Byte F1B Timer 3 Reload Low Byte F1C Timer 3 PWM High Byte F1D Timer 3 PWM Low Byte F1E Timer 3 Control 0 F1F Timer 3 Control 1 20-3F Reserved UART 0 F40 F41 F42 F43 F44 F45 F46 F47 UART 1 F48 F49 F4A F4B F4C F4D F4E F4F I2C F50 F51 F52 F53 F54 F55 F56 F57-F5F XX=Undefined UART0 Transmit Data UART0 Receive Data UART0 Status 0 UART0 Control 0 UART0 Control 1 UART0 Status 1 UART0 Address Compare Register UART0 Baud Rate High Byte UART0 Baud Rate Low Byte UART1 Transmit Data UART1 Receive Data UART1 Status 0 UART1 Control 0 UART1 Control 1 UART1 Status 1 UART1 Address Compare Register UART1 Baud Rate High Byte UART1 Baud Rate Low Byte I2C Data I2C Status I2C Control I2C Baud Rate High Byte I2C Baud Rate Low Byte I2C Diagnostic State I2C Diagnostic Control Reserved
109 110 110 112 112 110 115 115 115 109 110 110 112 112 110 115 115 115 152 153 155 156 156 158 160
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Table 7. 64K Series Register File Address Map (Continued) Address (Hex) Register Description Mnemonic SPIDATA SPICTL SPISTAT SPIMODE SPIDST -- SPIBRH SPIBRL -- ADCCTL -- ADCD_H ADCD_L -- DMA0CTL DMA0IO DMA0H DMA0START DMA0END DMA1CTL DMA1IO DMA1H DMA1START DMA1END Reset (Hex) XX 00 01 00 00 XX FF FF XX 20 XX XX XX XX 00 XX XX XX XX 00 XX XX XX XX Page # 133 133 135 136 137 138 138 Serial Peripheral Interface (SPI) F60 SPI Data F61 SPI Control F62 SPI Status F63 SPI Mode F64 SPI Diagnostic State F65 Reserved F66 SPI Baud Rate High Byte F67 SPI Baud Rate Low Byte F68-F6F Reserved Analog-to-Digital Converter (ADC) F70 ADC Control F71 Reserved F72 ADC Data High Byte F73 ADC Data Low Bits F74-FAF Reserved DMA 0 FB0 FB1 FB2 FB3 FB4 DMA 1 FB8 FB9 FBA FBB FBC DMA ADC FBD FBE FBF DMA0 Control DMA0 I/O Address DMA0 End/Start Address High Nibble DMA0 Start Address Low Byte DMA0 End Address Low Byte DMA1 Control DMA1 I/O Address DMA1 End/Start Address High Nibble DMA1 Start Address Low Byte DMA1 End Address Low Byte DMA_ADC Address DMA_ADC Control DMA_ADC Status
175 176 176
164 165 165 166 167 164 165 165 166 167 168 169 170 66 69 69 67 70 70 68
DMAA_ADDR XX DMAACTL 00 DMAASTAT 00 IRQ0 IRQ0ENH IRQ0ENL IRQ1 IRQ1ENH IRQ1ENL IRQ2 00 00 00 00 00 00 00
Interrupt Controller FC0 Interrupt Request 0 FC1 IRQ0 Enable High Bit FC2 IRQ0 Enable Low Bit FC3 Interrupt Request 1 FC4 IRQ1 Enable High Bit FC5 IRQ1 Enable Low Bit FC6 Interrupt Request 2 XX=Undefined
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Table 7. 64K Series Register File Address Map (Continued) Address (Hex) FC7 FC8 FC9-FCC FCD FCE FCF GPIO Port A FD0 FD1 FD2 FD3 GPIO Port B FD4 FD5 FD6 FD7 GPIO Port C FD8 FD9 FDA FDB GPIO Port D FDC FDD FDE FDF GPIO Port E FE0 FE1 FE2 FE3 GPIO Port F FE4 FE5 FE6 FE7 GPIO Port G FE8 FE9 FEA FEB XX=Undefined PS019915-1005 Register Description IRQ2 Enable High Bit IRQ2 Enable Low Bit Reserved Interrupt Edge Select Interrupt Port Select Interrupt Control Port A Address Port A Control Port A Input Data Port A Output Data Port B Address Port B Control Port B Input Data Port B Output Data Port C Address Port C Control Port C Input Data Port C Output Data Port D Address Port D Control Port D Input Data Port D Output Data Port E Address Port E Control Port E Input Data Port E Output Data Port F Address Port F Control Port F Input Data Port F Output Data Port G Address Port G Control Port G Input Data Port G Output Data Mnemonic IRQ2ENH IRQ2ENL -- IRQES IRQPS IRQCTL PAADDR PACTL PAIN PAOUT PBADDR PBCTL PBIN PBOUT PCADDR PCCTL PCIN PCOUT PDADDR PDCTL PDIN PDOUT PEADDR PECTL PEIN PEOUT PFADDR PFCTL PFIN PFOUT PGADDR PGCTL PGIN PGOUT Reset (Hex) 00 00 XX 00 00 00 00 00 XX 00 00 00 XX 00 00 00 XX 00 00 00 XX 00 00 00 XX 00 00 00 XX 00 00 00 XX 00 Page # 71 71 72 73 74 55 56 60 61 55 56 60 61 55 56 60 61 55 56 60 61 55 56 60 61 55 56 60 61 55 56 60 61
Register File Address Map
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Table 7. 64K Series Register File Address Map (Continued) Address (Hex) GPIO Port H FEC FED FEE FEF Register Description Port H Address Port H Control Port H Input Data Port H Output Data Mnemonic PHADDR PHCTL PHIN PHOUT WDTCTL WDTU WDTH WDTL -- FCTL FSTAT FPS FPROT FFREQH FFREQL -- RPS -- -- RP SPH SPL Reset (Hex) 00 00 XX 00 XXX00000b FF FF FF XX 00 00 00 00 00 00 XX 00 XX XX XX XX XX Refer to the eZ8 CPU User Manual Page # 55 56 60 61 94 95 95 95
Watch-Dog Timer (WDT) FF0 Watch-Dog Timer Control FF1 Watch-Dog Timer Reload Upper Byte FF2 Watch-Dog Timer Reload High Byte FF3 Watch-Dog Timer Reload Low Byte FF4--FF7 Reserved Flash Memory Controller FF8 Flash Control FF8 Flash Status FF9 Page Select FF9 (if enabled) Flash Sector Protect FFA Flash Programming Frequency High Byte FFB Flash Programming Frequency Low Byte FF4-FF8 Reserved Read-Only Memory Controller FF9 Page Select FFA-FFB Reserved eZ8 CPU FFC FFD FFE FFF XX=Undefined Flags Register Pointer Stack Pointer High Byte Stack Pointer Low Byte
185 186 187 188 189 189
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Control Register Summary
Timer 0 High Byte T0H (F00H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 current count value [15:8]
Timer 0 Control 1 T0CTL1 (F07H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = Capture/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled
Timer 0 Low Byte T0L (F01H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 current count value [7:0]
Timer 0 Reload High Byte T0RH (F02H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 reload value [15:8]
Timer 0 Reload Low Byte T0RL (HF03 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 reload value [7:0]
Timer 1 High Byte T1H (F08H - Read/Write) Timer 0 PWM High Byte T0PWMH (F04H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 0 PWM value [15:8] D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 current count value [15:8]
Timer 1 Low Byte T1L (F09H - Read/Write) Timer 0 Control 0 T0CTL0 (F06H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 0 Input signal is GPIO pin 1 = Timer 0 Input signal is Timer 3 out Reserved D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 current count value [7:0]
Timer 1 Reload High Byte T1RH (F0AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 reload value [15:8]
Timer 1 Reload Low Byte T1RL (F0BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 reload value [7:0]
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Timer 1 PWM High Byte T1PWMH (F0CH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 PWM value [15:8]
Timer 2 High Byte T2H (F10H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 current count value [15:8]
Timer 1 PWM Low Byte T1PWML (F0DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 1 PWM value [7:0]
Timer 2 Low Byte T2L (F11H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 current count value [7:0]
Timer 1 Control 0 T1CTL0 (F0EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 1 Input signal is GPIO pin 1 = Timer 1 Input signal is Timer 0 out Reserved
Timer 2 Reload High Byte T2RH (F12H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 reload value [15:8]
Timer 2 Reload Low Byte T2RL (F13H- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 reload value [7:0]
Timer 1 Control 1 T1CTL1 (F0FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = Capture/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled
Timer 2 PWM High Byte T2PWMH (F14H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 PWM value [15:8]
Timer 2 PWM Low Byte T2PWML (F15H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 2 PWM value [7:0]
Timer 2 Control 0 T2CTL0 (F16H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 2 Input signal is GPIO pin 1 = Timer 2 Input signal is Timer 1 out Reserved
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Timer 2 Control 1 T2CTL1 (F17H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = CAPTURE/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled
Timer 3 PWM High Byte T3PWMH (F1CH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 PWM value [15:8]
Timer 3 PWM Low Byte T3PWML (F1DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 PWM value [7:0]
Timer 3 Control 0 T3CTL0 (F1EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved Cascade Timer 0 = Timer 3 Input signal is GPIO pin 1 = Timer 3 Input signal is Timer 2 out Reserved
Timer 3 Control 1 T3CTL1 (F1FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer Mode 000 = One-Shot mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = Capture/COMPARE mode Prescale Value 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer Timer Enable 0 = Timer is disabled 1 = Timer is enabled
Timer 3 High Byte T3H (F18H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 current count value [15:8]
Timer 3 Low Byte T3L (F19H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 current count value [7:0]
Timer 3 Reload High Byte T3RH (F1AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 reload value [15:8]
Timer 3 Reload Low Byte T3RL (F1BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Timer 3 reload value [7:0]
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UART0 Transmit Data U0TXD (F40H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 transmitter data byte [7:0]
UART0 Control 0 U0CTL0 (F42H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Loop Back Enable 0 = Normal operation 1 = Transmit data is looped back to the receiver Stop Bit Select 0 = Transmitter sends 1 Stop bit 1 = Transmitter sends 2 Stop bits Send Break 0 = No break is sent 1 = Output of the transmitter is zero Parity Select 0 = Even parity 1 = Odd parity Parity Enable 0 = Parity is disabled 1 = Parity is enabled CTS Enable 0 = CTS signal has no effect on the transmitter 1 = UART recognizes CTS signal as a transmit enable control signal Receive Enable 0 = Receiver disabled 1 = Receiver enabled Transmit Enable 0 = Transmitter disabled 1 = Transmitter enabled
UART0 Receive Data U0RXD (F40H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 receiver data byte [7:0]
UART0 Status 0 U0STAT0 (F41H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 CTS signal Returns the level of the CTS signal Transmitter Empty 0 = Data is currently transmitting 1 = Transmission is complete Transmitter Data Register Empty 0 = Transmit Data Register is full 1 = Transmit Data register is empty Break Detect 0 = No break occurred 1 = A break occurred Framing Error 0 = No framing error occurred 1 = A framing occurred Overrun Error 0 = No overrun error occurred 1 = An overrun error occurred Parity Error 0 = No parity error occurred 1 = A parity error occurred Receive Data Available 0 = Receive Data Register is empty 1 = A byte is available in the Receive Data Register
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
30
UART0 Control 1 U0CTL1 (F43H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Infrared Encoder/Decoder Enable 0 = Infrared endec is disabled 1 = Infrared endec is enabled Received Data Interrupt Enable 0 = Received data and errors generate interrupt requests 1 = Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer to UART chapter for operation Driver Enable Polarity 0 = DE signal is active High 1 = DE signal is active Low Multiprocessor Bit Transmit 0 = Send a 0 as the multiprocessor bit 1 = Send a 1 as the multiprocessor bit Multiprocessor Mode [0] See Multiprocessor Mode [1] below Multiprocessor (9-bit) Enable 0 = Multiprocessor mode is disabled 1 = Multiprocessor mode is enabled Multiprocessor Mode [1] with Multiprocess Mode bit 0: 00 = Interrupt on all received bytes 01 = Interrupt only on address bytes 10 = Interrupt on address match and following data 11 = Interrupt on data following an address match
UART0 Baud Rate Generator High Byte U0BRH (F46H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 Baud Rate divisor [15:8]
UART0 Baud Rate Generator Low Byte U0BRL (F47H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 Baud Rate divisor [7:0]
UART1 Transmit Data U1TXD (F48H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0 UART1 transmitter data byte[7:0]
UART1 Receive Data U1RXD (F48H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 UART receiver data byte [7:0]
UART0 Status 1 U0STAT1 (F44H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Mulitprocessor Receive Returns value of last multiprocessor bit New Frame 0 = Current byte is not start of frame 1 = Current byte is start of new frame Reserved
UART0 Address Compare U0ADDR (F45H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 UART0 Address Compare [7:0]
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
31
UART1 Status 0 U1STAT0 (F49H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 CTS signal Returns the level of the CTS signal Transmitter Empty 0 = Data is currently transmitting 1 = Transmission is complete Transmitter Data Register Empty 0 = Transmit Data Register is full 1 = Transmit Data register is empty Break Detect 0 = No break occurred 1 = A break occurred Framing Error 0 = No framing error occurred 1 = A framing occurred Overrun Error 0 = No overrun error occurred 1 = An overrun error occurred Parity Error 0 = No parity error occurred 1 = A parity error occurred Receive Data Available 0 = Receive Data Register is empty 1 = A byte is available in the Receive Data Register
UART1 Control 0 U1CTL0 (F4AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Loop Back Enable 0 = Normal operation 1 = Transmit data is looped back to the receiver Stop Bit Select 0 = Transmitter sends 1 Stop bit 1 = Transmitter sends 2 Stop bits Send Break 0 = No break is sent 1 = Output of the transmitter is zero Parity Select 0 = Even parity 1 = Odd parity Parity Enable 0 = Parity is disabled 1 = Parity is enabled CTS Enable 0 = CTS signal has no effect on the transmitter 1 = UART recognizes CTS signal as a transmit enable control signal Receive Enable 0 = Receiver disabled 1 = Receiver enabled Transmit Enable 0 = Transmitter disabled 1 = Transmitter enabled
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
32
UART1 Control 1 U0CTL1 (F4BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Infrared Encoder/Decoder Enable 0 = Infrared endec is disabled 1 = Infrared endec is enabled Received Data Interrupt Enable 0 = Received data and errors generate interrupt requests 1 = Only errors generate interrupt requests. Received data does not. Baud Rate Registers Control Refer to UART chapter for operation Driver Enable Polarity 0 = DE signal is active High 1 = DE signal is active Low Multiprocessor Bit Transmit 0 = Send a 0 as the multiprocessor bit 1 = Send a 1 as the multiprocessor bit Multiprocessor Mode [0] See Multiprocessor Mode [1] below Multiprocessor (9-bit) Enable 0 = Multiprocessor mode is disabled 1 = Multiprocessor mode is enabled Multiprocessor Mode [1] with Multiprocess Mode bit 0: 00 = Interrupt on all received bytes 01 = Interrupt only on address bytes 10 = Interrupt on address match and following data 11 = Interrupt on data following an address match
UART1 Baud Rate Generator High Byte U0BRH (F4EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 UART1 Baud Rate divisor [15:8]
UART1 Baud Rate Generator Low Byte U1BRL (F4FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 UART1 Baud Rate divisor [7:0]
I2C Data I2CDATA (F50H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 I2C data [7:0]
I2C Status I2CSTAT (F51H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 NACK Interrupt 0 = No action required to service NAK 1 = START/STOP not set after NAK Data Shift State 0 = Data is not being transferred 1 = Data is being transferred Transmit Address State 0 = Address is not being transferred 1 = Address is being transferred Read 0 = Write operation 1 = Read operation 10-Bit Address 0 = 7-bit address being transmitted 1 = 10-bit address being transmitted Acknowledge 0 = Acknowledge not transmitted/received 1 = For last byte, Acknowledge was transmitted/received Receive Data Register Full 0 = I2C has not received data 1 = Data register contains received data Transmit Data Register Empty 0 = Data register is full 1 = Data register is empty
UART1 Status 1 U0STAT1 (F4CH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Mulitprocessor Receive Returns value of last multiprocessor bit New Frame 0 = Current byte is not start of frame 1 = Current byte is start of new frame Reserved
UART1 Address Compare U0ADDR (F4DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 UART1 Address Compare [7:0]
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
33
I2C Control I2CCTL (F52H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 I2C Signal Filter Enable 0 = Digital filtering disabled 1 = Low-pass digital filters enabled on SDA and SCL input signals Flush Data 0 = No effect 1 = Clears I2C Data register Send NAK 0 = Do not send NAK 1 = Send NAK after next byte received from slave Enable TDRE Interrupts 0 = Do not generate an interrupt when the I2C Data register is empty 1 = Generate an interrupt when the I2C Transmit Data register is empty Baud Rate Generator Interrupt Request 0 = Interrupts behave as set by I2C control 1 = BRG generates an interrupt when it counts down to zero Send Stop Condition 0 = Do not issue Stop condition after data transmission is complete 1 = Issue Stop condition after data transmission is complete Send Start Condition 0 = Do not send Start Condition 1 = Send Start Condition I2C Enable 0 = I2C is disabled 1 = I2C is enabled
SPI Data SPIDATA (F60H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 SPI Data [7:0]
SPI Control SPICTL (F61H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 SPI Enable 0 = SPI disabled 1 = SPI enabled Master Mode Enabled 0 = SPI configured in Slave mode 1 = SPI configured in Master mode Wire-OR (open-drain) Mode Enabled 0 = SPI signals not configured for open-drain 1 = SPI signals (SCK, SS, MISO, and MOSI) configured for open-drain Clock Polarity 0 = SCK idles Low 1 = SPI idles High Phase Select Sets the phase relationship of the data to the clock. BRG Timer Interrupt Request 0 = BRG timer function is disabled 1 = BRG time-out interrupt is enabled Start an SPI Interrupt Request 0 = No effect 1 = Generate an SPI interrupt request Interrupt Request Enable 0 = SPI interrupt requests are disabled 1 = SPI interrupt requests are enabled
I2C Baud Rate Generator High Byte I2CBRH (F53H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 I2C Baud Rate divisor [15:8]
I2C Baud Rate Generator Low Byte I2CBRL (F54H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 I2C Baud Rate divisor [7:0]
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
34
SPI Status SPISTAT (F62H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Slave Select 0 = If Slave, SS pin is asserted 1 = If Slave, SS pin is not asserted Transmit Status 0 = No data transmission in progress 1 = Data transmission now in progress Reserved Slave Mode Transaction Abort 0 = No slave mode transaction abort detected 1 = Slave mode transaction abort was detected Collision 0 = No multi-master collision detected 1 = Multi-master collision was detected Overrun 0 = No overrun error detected 1 = Overrun error was detected Interrupt Request 0 = No SPI interrupt request pending 1 = SPI interrupt request is pending
SPI Diagnostic State SPIDST (F64H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 SPI State Transmit Clock Enable 0 = Internal transmit clock enable signal is deasserted 1 = Internal transmit clock enable signal is asserted Shift Clock Enable 0 = Internal shift clock enable signal is deasserted 1 = Internal shift clock enable signal is asserted
SPI Baud Rate Generator High Byte SPIBRH (F66H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 SPI Baud Rate divisor [15:8]
SPI Baud Rate Generator Low Byte SPIBRL (F67H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 SPI Baud Rate divisor [7:0]
SPI Mode SPIMODE (F63H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Slave Select Value If Master and SPIMODE[1] = 1: 0 = SS pin driven Low 1 = SS pin driven High Slave Select I/O 0 = SS pin configured as an input 1 = SS pin configured as an output (Master mode only) Number of Data Bits Per Character 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bit 110 = 6 bits 111 = 7 bits Diagnostic Mode Control 0 = Reading from SPIBRH, SPIBRL returns reload values 1 = Reading from SPIBRH, SPIBRL returns current BRG count value Reserved
ADC Control ADCCTL (F70H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Analog Input Select 0000 = ANA0 0001 = ANA1 0010 = ANA2 0011 = ANA3 0100 = ANA4 0101 = ANA5 0110 = ANA6 0111 = ANA7 1000 = ANA8 1001 = ANA9 1010 = ANA10 1011 = ANA11 11xx = Reserved Continuous Mode Select 0 = Single-shot conversion 1 = Continuous conversion External VREF select 0 = Internal voltage reference selected 1 = External voltage reference selected Reserved Conversion Enable 0 = Conversion is complete 1 = Begin conversion
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
35
ADC Data High Byte ADCD_H (F72H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 ADC Data [9:2]
DMA0 Address High Nibble DMA0H (FB2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Start Address [11:8] DMA0 End Address [11:8]
ADC Data Low Bits ADCD_L (F73H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved ADC Data [1:0]
DMA0 Start/Current Address Low Byte DMA0START (FB3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Start Address [7:0]
DMA0 Control DMA0CTL (FB0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Request Trigger Source Select 000 = Timer 0 001 = Timer 1 010 = Timer 2 011 = Timer 3 100 = UART0 Received Data register contains valid data 101 = UART1 Received Data register contains valid data 110 = I2C receiver contains valid data 111 = Reserved Word Select 0 = DMA transfers 1 byte per request 1 = DMA transfers 2 bytes per request DMA0 Interrupt Enable 0 = DMA0 does not generate interrupts 1 = DMA0 generates an interrupt when End Address data is transferred DMA0 Data Transfer Direction 0 = Register File to peripheral registers 1 = Peripheral registers to Register File DMA0 Loop Enable 0 = DMA disables after End Address 1 = DMA reloads Start Address after End Address and continues to run DMA0 Enable 0 = DMA0 is disabled 1 = DMA0 is enabled
DMA0 End Address Low Byte DMA0END (FB4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 DMA0 End Address [7:0]
DMA1 Control DMA1CTL (FB8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Request Trigger Source Select 000 = Timer 0 001 = Timer 1 010 = Timer 2 011 = Timer 3 100 = UART0 Transmit Data register is empty 101 = UART1 Transmit Data register is empty 110 = I2C Transmit Data register is empty 111 = Reserved Word Select 0 = DMA transfers 1 byte per request 1 = DMA transfers 2 bytes per request DMA1 Interrupt Enable 0 = DMA1 does not generate interrupts 1 = DMA1 generates an interrupt when End Address data is transferred DMA1 Data Transfer Direction 0 = Register File to peripheral registers 1 = Peripheral registers to Register File DMA1 Loop Enable 0 = DMA disables after End Address 1 = DMA reloads Start Address after End Address and continues to run DMA1 Enable 0 = DMA1 is disabled 1 = DMA1 is enabled
DMA0 I/O Address DMA0IO (FB1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Peripheral Register Address Low byte of on-chip peripheral control registers on Register File page FH
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
36
DMA1 I/O Address DMA1IO (FB9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 DMA1 Peripheral Register Address Low byte of on-chip peripheral control registers on Register File page FH
DMA_ADC Control DMAACTL (FBEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 ADC Analog Input Number 0000 = Analog input 0 updated 0001 = Analog input 0-1 updated 0010 = Analog input 0-2 updated 0011 = Analog input 0-3 updated 0100 = Analog input 0-4 updated 0101 = Analog input 0-5 updated 0100 = Analog input 0-6 updated 0101 = Analog input 0-7 updated 1000 = Analog input 0-8 updated 1001 = Analog input 0-9 updated 1010 = Analog input 0-10 updated 1011 = Analog inputs 0-11 updated 11xx = Reserved Reserved
DMA1 Address High Nibble DMA1H (FBAH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 DMA1 Start Address [11:8] DMA1 End Address [11:8]
DMA1 Start/Current Address Low Byte DMA1START (FBBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 DMA1 Start Address [7:0]
Interrupt request enable 0 = DMA_ADC does not generate interrupt requests 1 = DMA_ADC generates interrupt requests after last analog input DMA_ADC Enable 0 = DMA_ADC is disabled 1 = DMA_ADC is enabled
DMA1 End Address Low Byte DMA1END (FBCH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 DMA1 End Address [7:0]
DMA Status DMAA_STAT (FBFH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 DMA0 Interrupt Request Indicator 0 = DMA0 is not the source of the IRQ 1 = DMA0 is the source of the IRQ DMA1 Interrupt Request Indicator 0 = DMA1 is not the source of the IRQ 1 = DMA1 is the source of the IRQ DMA_ADC Interrupt Request Indicator 0 = DMA_ADC is not the source of the IRQ 1 = DMA_ADC is the source of the IRQ Reserved Current ADC analog input Identifies the analog input the ADC is currently converting
DMA_ADC Address DMAA_ADDR (FBDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved DMA_ADC Address
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
37
Interrupt Request 0 IRQ0 (FC0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 ADC Interrupt Request SPI Interrupt Request I2C Interrupt Request UART 0 Transmitter Interrupt Request UART 0 Receiver Interrupt Request Timer 0 Interrupt Request Timer 1 Interrupt Request Timer 2 Interrupt Request For all of the above peripherals: 0 = Peripheral IRQ is not pending 1 = Peripheral IRQ is awaiting service
IRQ0 Enable Low Bit IRQ0ENL (FC2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 ADC IRQ Enable Hit Bit SPI IRQ Enable Low Bit I2C IRQ Enable Low Bit UART 0 Transmitter IRQ Enable Low UART 0 Receiver IRQ Enable Low Bit Timer 0 IRQ Enable Low Bit Timer 1 IRQ Enable Low Bit Timer 2 IRQ Enable Low Bit
Interrupt Request 1 IRQ1 (FC3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Pin Interrupt Request 0 = IRQ from corresponding pin [7:0] is not pending 1 = IRQ from corresponding pin [7:0] is awaiting service
IRQ0 Enable High Bit IRQ0ENH (FC1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 ADC IRQ Enable Hit Bit SPI IRQ Enable High Bit I2C IRQ Enable High Bit UART 0 Transmitter IRQ Enable High UART 0 Receiver IRQ Enable High Bit Timer 0 IRQ Enable High Bit Timer 1 IRQ Enable High Bit Timer 2 IRQ Enable High Bit
IRQ1 Enable High Bit IRQ1ENH (FC4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Pin IRQ Enable High Bit
IRQ1 Enable Low Bit IRQ1ENL (FC5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Pin IRQ Enable Low Bit
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
38
Interrupt Request 2 IRQ2 (FC6H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin Interrupt Request 0 = IRQ from corresponding pin [3:0] is not pending 1 = IRQ from corresponding pin [3:0] is awaiting service DMA Interrupt Request UART 1 Transmitter Interrupt Request UART 1 Receiver Interrupt Request Timer 3 Interrupt Request For all of the above peripherals: 0 = Peripheral IRQ is not pending 1 = Peripheral IRQ is awaiting service
Interrupt Port Select IRQPS (FCEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Port Pin Select [7:0] 0 = Port A pin is the interrupt source 1 = Port D pin is the interrupt source
Interrupt Control IRQCTL (FCFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Reserved Interrupt Request Enable 0 = Interrupts are disabled 1 = Interrupts are enabled
IRQ2 Enable High Bit IRQ2ENH (FC7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin IRQ Enable High Bit DMA IRQ Enable High Bit UART 1 Transmitter IRQ Enable High UART 1 Receiver IRQ Enable High Bit Timer 3 IRQ Enable High Bit
Port A Address PAADDR (FD0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function
IRQ2 Enable Low Bit IRQ2ENL (FC8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Pin IRQ Enable Low Bit DMA IRQ Enable Low Bit UART 1 Transmitter IRQ Enable Low UART 1 Receiver IRQ Enable Low Bit Timer 3 IRQ Enable Low Bit
Port A Control PACTL (FD1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Control[7:0] Provides Access to Port Sub-Registers
Port A Input Data PAIN (FD2H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Input Data [7:0]
Interrupt Edge Select IRQES (FCDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A or D Interrupt Edge Select [7:0] 0 = Falling edge 1 = Rising edge
Port A Output Data PAOUT (FD3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port A Output Data [7:0]
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
39
Port B Address PBADDR (FD4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port B Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function
Port C Input Data PCIN (FDAH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Input Data [7:0]
Port C Output Data PCOUT (FDBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Output Data [7:0]
Port B Control PBCTL (FD5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port B Control[7:0] Provides Access to Port Sub-Registers
Port D Address PDADDR (FDCH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port D Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function
Port B Input Data PBIN (FD6H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port B Input Data [7:0]
Port B Output Data PBOUT (FD7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port B Output Data [7:0]
Port D Control PDCTL (FDDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port D Control[7:0] Provides Access to Port Sub-Registers
Port C Address PCADDR (FD8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function
Port D Input Data PDIN (FDE H- Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port D Input Data [7:0]
Port D Output Data PDOUT (FDFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port D Output Data [7:0]
Port C Control PCCTL (FD9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port C Control[7:0] Provides Access to Port Sub-Registers
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
40
Port E Address PEADDR (FE0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port E Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function
Port F Input Data PFIN (FE6H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port F Input Data [7:0]
Port F Output Data PFOUT (FE7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port F Output Data [7:0]
Port E Control PECTL (FE1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port E Control[7:0] Provides Access to Port Sub-Registers
Port G Address PGADDR (FE8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port G Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function
Port E Input Data PEIN (FE2H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port E Input Data [7:0]
Port E Output Data PEOUT (FE3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port E Output Data [7:0]
Port G Control PGCTL (FE9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port G Control[7:0] Provides Access to Port Sub-Registers
Port F Address PFADDR (FE4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port F Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function
Port G Input Data PGIN (FEAH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port G Input Data [7:0]
Port G Output Data PGOUT (FEBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port G Output Data [7:0]
Port F Control PFCTL (FE5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port F Control[7:0] Provides Access to Port Sub-Registers
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
41
Port H Address PHADDR (FECH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port H Address[7:0] Selects Port Sub-Registers: 00H = No function 01H = Data direction 02H = Alternate function 03H = Output control (open-drain) 04H = High drive enable 05H = STOP mode recovery enable 06H-FFH = No function
Watch-Dog Timer Control WDTCTL (FF0H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 SM Configuration Indicator Reserved EXT 0 = Reset not generated by RESET pin 1 = Reset generated by RESET pin WDT 0 = WDT timeout has not occurred 1 = WDT timeout occurred STOP 0 = SMR has not occurred 1 = SMR has occurred POR 0 = POR has not occurred 1 = POR has occurred
Port H Control PHCTL (FEDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port H Control [3:0] Provides Access to Port Sub-Registers Reserved
Watch-Dog Timer Reload Upper Byte WDTU (FF1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [23:16]
Port H Input Data PHIN (FEEH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Port H Input Data [3:0] Reserved
Watch-Dog Timer Reload Middle Byte WDTH (FF2 H- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [15:8]
Port H Output Data PHOUT (FEFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Port H Output Data [3:0] Reserved
Watch-Dog Timer Reload Low Byte WDTL (FF3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 WDT reload value [7:0]
Flash Control FCTL (FF8H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Command 73H = First unlock command 8CH = Second unlock command 95H = Page erase command 63H = Mass erase command 5EH = Flash Sector Protect reg select
PS019915-1005
Control Register Summary
Z8 Encore!(R) 64K Series Z8 Encore!
42
Flash Status FSTAT (FF8H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Controller Status 00_0000 = Flash controller locked 00_0001 = First unlock received 00_0010 = Second unlock received 00_0011 = Flash controller unlocked 00_0100 = Flash Sector Protect register selected 00_1xxx = Programming in progress 01_0xxx = Page erase in progress 10_0xxx = Mass erase in progress Reserved
Flags FLAGS (FFC - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 F1 - User Flag 1 F2 - User Flag 2 H - Half Carry D - Decimal Adjust V - Overflow Flag S - Sign Flag Z - Zero Flag
Page Select FPS (FF9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Page Select [6:0] Identifies the Flash memory page for Page Erase operation. Information Area Enable 0 = Information Area access is disabled 1 = Information Area access is enabled
C - Carry Flag
Register Pointer RP (FFDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Working Register Page Address [11:8] Working Register Group Address [7:4]
Flash Sector Protect FPROT (FF9H - Read/Write to 1's)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Sector Protect [7:0] 0 = Sector can be programmed or erased from user code 1 = Sector is protected and cannot be programmed or erased from user code
Stack Pointer High Byte SPH (FFEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer [15:8]
Stack Pointer Low Byte SPL (FFFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer [7:0]
Flash Frequency High Byte FFREQH (FFAH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Frequency value [15:8]
Flash Frequency Low Byte FFREQL (FFBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0 Flash Frequency value [7:0]
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Reset and STOP Mode Recovery
Overview
The Reset Controller within the Z8 Encore!(R) 64K Series controls Reset and STOP Mode Recovery operation. In typical operation, the following events cause a Reset to occur:
* * * * *
Power-On Reset (POR) Voltage Brown-Out (VBO) Watch-Dog Timer time-out (when configured via the WDT_RES Option Bit to initiate a Reset) External RESET pin assertion On-Chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the 64K Series devices are in STOP mode, a STOP Mode Recovery is initiated by either of the following:
* * * Reset Types
Watch-Dog Timer time-out GPIO Port input pin transition on an enabled STOP Mode Recovery source DBG pin driven Low
The 64K Series provides two different types of reset operation (System Reset and STOP Mode Recovery). The type of Reset is a function of both the current operating mode of the 64K Series devices and the source of the Reset. Table 8 lists the types of Reset and their operating characteristics.
Table 8. Reset and STOP Mode Recovery Characteristics and Latency Reset Characteristics and Latency Reset Type System Reset STOP Mode Recovery Control Registers Reset (as applicable) Unaffected, except WDT_CTL register eZ8 CPU Reset Latency (Delay) Reset Reset 66 WDT Oscillator cycles + 16 System Clock cycles 66 WDT Oscillator cycles + 16 System Clock cycles
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System Reset During a System Reset, the 64K Series devices are held in Reset for 66 cycles of the Watch-Dog Timer oscillator followed by 16 cycles of the system clock. At the beginning of Reset, all GPIO pins are configured as inputs. During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal oscillator and Watch-Dog Timer oscillator continue to run. The system clock begins operating following the Watch-Dog Timer oscillator cycle count. The eZ8 CPU and on-chip peripherals remain idle through the 16 cycles of the system clock. Upon Reset, control registers within the Register File that have a defined Reset value are loaded with their reset values. Other control registers (including the Stack Pointer, Register Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter. Program execution begins at the Reset vector address.
Reset Sources
Table 9 lists the reset sources as a function of the operating mode. The text following provides more detailed information on the individual Reset sources. A Power-On Reset/Voltage Brown-Out event always takes priority over all other possible reset sources to ensure a full system reset occurs.
Table 9. Reset Sources and Resulting Reset Type Operating Mode Normal or HALT modes Reset Source Reset Type
Power-On Reset / Voltage Brown-Out System Reset Watch-Dog Timer time-out when configured for Reset RESET pin assertion On-Chip Debugger initiated Reset (OCDCTL[0] set to 1) System Reset System Reset System Reset except the On-Chip Debugger is unaffected by the reset
STOP mode
Power-On Reset / Voltage Brown-Out System Reset RESET pin assertion DBG pin driven Low System Reset System Reset
Power-On Reset
Each device in the 64K Series contains an internal Power-On Reset (POR) circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
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voltage threshold (VPOR), the POR Counter is enabled and counts 66 cycles of the WatchDog Timer oscillator. After the POR counter times out, the XTAL Counter is enabled to count a total of 16 system clock pulses. The devices are held in the Reset state until both the POR Counter and XTAL counter have timed out. After the 64K Series devices exit the Power-On Reset state, the eZ8 CPU fetches the Reset vector. Following Power-On Reset, the POR status bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1. Figure 8 illustrates Power-On Reset operation. Refer to the Electrical Characteristics chapter for the POR threshold voltage (VPOR).
VCC = 3.3V VPOR VVBO
VCC = 0.0V
Program Execution
WDT Clock
Primary Oscillator Oscillator Start-up
Internal RESET signal
Not to Scale
POR counter delay
XTAL counter delay
Figure 8. Power-On Reset Operation)
Voltage Brown-Out Reset
The devices in the 64K Series provide low Voltage Brown-Out (VBO) protection. The VBO circuit senses when the supply voltage drops to an unsafe level (below the VBO threshold voltage) and forces the device into the Reset state. While the supply voltage remains below the Power-On Reset voltage threshold (VPOR), the VBO block holds the device in the Reset state. After the supply voltage again exceeds the Power-On Reset voltage threshold, the devices progress through a full System Reset sequence, as described in the Power-On Reset sec-
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tion. Following Power-On Reset, the POR status bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1. Figure 9 illustrates Voltage Brown-Out operation. Refer to the Electrical Characteristics chapter for the VBO and POR threshold voltages (VVBO and VPOR). The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode. Operation during STOP mode is set by the VBO_AO Option Bit. Refer to the Option Bits chapter for information on configuring VBO_AO.
VCC = 3.3V VPOR VVBO Program Execution Voltage Brownout Program Execution
VCC = 3.3V
WDT Clock
Primary Oscillator
Internal RESET Signal
POR Counter Delay
XTAL Counter Delay
Figure 9. Voltage Brown-Out Reset Operation
Watch-Dog Timer Reset
If the device is in normal or HALT mode, the Watch-Dog Timer can initiate a System Reset at time-out if the WDT_RES Option Bit is set to 1. This capability is the default (unprogrammed) setting of the WDT_RES Option Bit. The WDT status bit in the WDT Control register is set to signify that the reset was initiated by the Watch-Dog Timer.
External Pin Reset
The RESET pin has a Schmitt-triggered input, an internal pull-up, an analog filter and a digital filter to reject noise. Once the RESET pin is asserted for at least 4 system clock
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cycles, the devices progress through the System Reset sequence. While the RESET input pin is asserted Low, the 64K Series devices continue to be held in the Reset state. If the RESET pin is held Low beyond the System Reset time-out, the devices exit the Reset state immediately following RESET pin deassertion. Following a System Reset initiated by the external RESET pin, the EXT status bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip goes through a normal system reset. The RST bit automatically clears during the system reset. Following the system reset the POR bit in the WDT Control register is set.
STOP Mode Recovery
STOP mode is entered by the eZ8 executing a STOP instruction. Refer to the Section Low-Power Modes on page 49 for detailed STOP mode information. During STOP Mode Recovery, the devices are held in reset for 66 cycles of the Watch-Dog Timer oscillator followed by 16 cycles of the system clock. STOP Mode Recovery only affects the contents of the Watch-Dog Timer Control register. STOP Mode Recovery does not affect any other values in the Register File, including the Stack Pointer, Register Pointer, Flags, peripheral control registers, and general-purpose RAM. The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter. Program execution begins at the Reset vector address. Following STOP Mode Recovery, the STOP bit in the Watch-Dog Timer Control Register is set to 1. Table 10 lists the STOP Mode Recovery sources and resulting actions. The text following provides more detailed information on each of the STOP Mode Recovery sources.
Table 10. STOP Mode Recovery Sources and Resulting Action Operating Mode STOP mode STOP Mode Recovery Source Watch-Dog Timer time-out when configured for Reset Watch-Dog Timer time-out when configured for interrupt Data transition on any GPIO Port pin enabled as a STOP Mode Recovery source Action STOP Mode Recovery STOP Mode Recovery followed by interrupt (if interrupts are enabled) STOP Mode Recovery
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STOP Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during STOP mode, the device undergoes a STOP Mode Recovery sequence. In the Watch-Dog Timer Control register, the WDT and STOP bits are set to 1. If the Watch-Dog Timer is configured to generate an interrupt upon timeout and the 64K Series devices are configured to respond to interrupts, the eZ8 CPU services the Watch-Dog Timer interrupt request following the normal STOP Mode Recovery sequence.
STOP Mode Recovery Using a GPIO Port Pin Transition HALT
Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source. On any GPIO pin enabled as a STOP Mode Recovery source, a change in the input pin value (from High to Low or from Low to High) initiates STOP Mode Recovery. The GPIO STOP Mode Recovery signals are filtered to reject pulses less than 10ns (typical) in duration. In the Watch-Dog Timer Control register, the STOP bit is set to 1. Caution: In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input Data registers record the Port transition only if the signal stays on the Port pin through the end of the STOP Mode Recovery delay. Thus, short pulses on the Port pin can initiate STOP Mode Recovery without being written to the Port Input Data register or without initiating an interrupt (if enabled for that pin).
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Low-Power Modes
Overview
The 64K Series products contain power-saving features. The highest level of power reduction is provided by STOP mode. The next level of power reduction is provided by the HALT mode.
STOP Mode
Execution of the eZ8 CPU's STOP instruction places the device into STOP mode. In STOP mode, the operating characteristics are:
* * * * * * *
Primary crystal oscillator is stopped; the XIN pin is driven High and the XOUT pin is driven Low. System clock is stopped eZ8 CPU is stopped Program counter (PC) stops incrementing The Watch-Dog Timer and its internal RC oscillator continue to operate, if enabled for operation during STOP mode. The Voltage Brown-Out protection circuit continues to operate, if enabled for operation in STOP mode using the associated Option Bit. All other on-chip peripherals are idle.
To minimize current in STOP mode, all GPIO pins that are configured as digital inputs must be driven to one of the supply rails (VCC or GND), the Voltage Brown-Out protection must be disabled, and the Watch-Dog Timer must be disabled. The devices can be brought out of STOP mode using STOP Mode Recovery. For more information on STOP Mode Recovery refer to the Reset and STOP Mode Recovery chapter beginning on page 43. Caution: STOP Mode must not be used when driving the 64K Series devices with an external clock driver source.
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HALT Mode
Execution of the eZ8 CPU's HALT instruction places the device into HALT mode. In HALT mode, the operating characteristics are:
* * * * * * * * * * * *
Primary crystal oscillator is enabled and continues to operate System clock is enabled and continues to operate eZ8 CPU is stopped Program counter (PC) stops incrementing Watch-Dog Timer's internal RC oscillator continues to operate The Watch-Dog Timer continues to operate, if enabled All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of HALT mode by any of the following operations: Interrupt Watch-Dog Timer time-out (interrupt or reset) Power-on reset Voltage-brown out reset External RESET pin assertion
To minimize current in HALT mode, all GPIO pins which are configured as inputs must be driven to one of the supply rails (VCC or GND).
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General-Purpose I/O
Overview
The 64K Series products support a maximum of seven 8-bit ports (Ports A-G) and one 4bit port (Port H) for general-purpose input/output (I/O) operations. Each port contains control and data registers. The GPIO control registers are used to determine data direction, open-drain, output drive current and alternate pin functions. Each port pin is individually programmable. All ports (except B and H) support 5V-tolerant inputs.
GPIO Port Availability By Device
Table 11 lists the port pins available with each device and package type.
Table 11. Port Availability by Device and Package Type Device Z8X1621 Z8X1621 Z8X1622 Z8X2421 Z8X2421 Z8X2422 Z8X3221 Z8X3221 Z8X3222 Z8X4821 Z8X4821 Z8X4822 Z8X4823 Packages 40-pin 44-pin 64- and 68-pin 40-pin 44-pin 64- and 68-pin 40-pin 44-pin 64- and 68-pin 40-pin 44-pin 64- and 68-pin 80-pin Port A [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Port B [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] Port C [6:0] [7:0] [7:0] [6:0] [7:0] [7:0] [6:0] [7:0] [7:0] [6:0] [7:0] [7:0] [7:0] Port D [6:3, 1:0] [6:0] [7:0] [6:3, 1:0] [6:0] [7:0] [6:3, 1:0] [6:0] [7:0] [6:3, 1:0] [6:0] [7:0] [7:0] Port E [7:0] [7:0] [7:0] [7:0] [7:0] Port F [7] [7] [7] [7] [7:0] Port G [3] [3] [3] [3] [7:0] Port H [3:0] [3:0] [3:0] [3:0] [3:0]
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Table 11. Port Availability by Device and Package Type (Continued) Device Z8X6421 Z8X6421 Z8X6422 Z8X6423 Packages 40-pin 44-pin 64- and 68-pin 80-pin Port A [7:0] [7:0] [7:0] [7:0] Port B [7:0] [7:0] [7:0] [7:0] Port C [6:0] [7:0] [7:0] [7:0] Port D [6:3, 1:0] [6:0] [7:0] [7:0] Port E [7:0] [7:0] Port F [7] [7:0] Port G [3] [7:0] Port H [3:0] [3:0]
Architecture
Figure 10 illustrates a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions and variable port current drive strength are not illustrated.
Port Input Data Register Q D Schmitt Trigger
System Clock VDD Port Output Control Port Output Data Register DATA Bus System Clock D Q Port Pin
Port Data Direction GND
Figure 10. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used as both general-purpose I/O and to provide access to on-chip peripheral functions such as the timers and serial communication devices. The Port A-H Alternate Function sub-registers configure these pins for either general-purpose
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I/O or alternate function operation. When a pin is configured for alternate function, control of the port pin direction (input/output) is passed from the Port A-H Data Direction registers to the alternate function assigned to this pin. Table 12 lists the alternate functions associated with each port pin.
Table 12. Port Alternate Function Mapping Port Port A Pin PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Port B PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Port C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Mnemonic T0IN T0OUT DE0 CTS0 Alternate Function Description Timer 0 Input Timer 0 Output UART 0 Driver Enable UART 0 Clear to Send
RXD0 / IRRX0 UART 0 / IrDA 0 Receive Data TXD0 / IRTX0 SCL SDA ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 T1IN T1OUT SS SCK MOSI MISO T2IN T2OUT UART 0 / IrDA 0 Transmit Data I2C Clock (automatically open-drain) I2C Data (automatically open-drain) ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 ADC Analog Input 4 ADC Analog Input 5 ADC Analog Input 6 ADC Analog Input 7 Timer 1 Input Timer 1 Output SPI Slave Select SPI Serial Clock SPI Master Out Slave In SPI Master In Slave Out Timer 2 In Timer 2 Out
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Table 12. Port Alternate Function Mapping (Continued) Port Port D Pin PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Port E Port F Port G Port H Mnemonic T3IN T3OUT N/A DE1 Alternate Function Description Timer 3 In (unavailable in 44-pin packages) Timer 3 Out (unavailable in 44-pin packages) No alternate function UART 1 Driver Enable
RXD1 / IRRX1 UART 1 / IrDA 1 Receive Data TXD1 / IRTX1 CTS1 RCOUT UART 1 / IrDA 1 Transmit Data UART 1 Clear to Send Watch-Dog Timer RC Oscillator Output No alternate functions No alternate functions No alternate functions ADC Analog Input 8 ADC Analog Input 9 ADC Analog Input 10 ADC Analog Input 11
PE[7:0] N/A PF[7:0] N/A PG[7:0] N/A PH0 PH1 PH2 PH3 ANA8 ANA9 ANA10 ANA11
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be configured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. Other port pin interrupts generate an interrupt when any edge occurs (both rising and falling). Refer to the Interrupt Controller chapter for more information on interrupts using the GPIO pins.
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data. Table 13 lists these Port registers. Use the Port A-H Address and Control registers together to provide access to sub-registers for Port configuration and control.
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Table 13. GPIO Port Registers and Sub-Registers Port Register Mnemonic PxADDR PxCTL PxIN PxOUT Port Sub-Register Mnemonic PxDD PxAF PxOC PxDD PxSMRE Port Register Name Port A-H Address Register (Selects sub-registers) Port A-H Control Register (Provides access to sub-registers) Port A-H Input Data Register Port A-H Output Data Register Port Register Name Data Direction Alternate Function Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable
Port A-H Address Registers
The Port A-H Address registers select the GPIO Port functionality accessible through the Port A-H Control registers. The Port A-H Address and Control registers combine to provide access to all GPIO Port control (Table 14).
Table 14. Port A-H GPIO Address Registers (PxADDR)
BITS FIELD RESET R/W ADDR
7
6
5
4
3
2
1
0
PADDR[7:0] 00H R/W FD0H, FD4H, FD8H, FDCH, FE0H, FE4H, FE8H, FECH
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PADDR[7:0]--Port Address The Port Address selects one of the sub-registers accessible through the Port Control register.
PADDR[7:0] 00H 01H 02H 03H 04H 05H 06H-FFH Port Control sub-register accessible using the Port A-H Control Registers No function. Provides some protection against accidental Port reconfiguration. Data Direction Alternate Function Output Control (Open-Drain) High Drive Enable STOP Mode Recovery Source Enable. No function.
Port A-H Control Registers
The Port A-H Control registers set the GPIO port operation. The value in the corresponding Port A-H Address register determines the control sub-registers accessible using the Port A-H Control register (Table 15).
Table 15. Port A-H Control Registers (PxCTL)
BITS FIELD RESET R/W ADDR
7
6
5
4
PCTL 00H R/W
3
2
1
0
FD1H, FD5H, FD9H, FDDH, FE1H, FE5H, FE9H, FEDH
PCTL[7:0]--Port Control The Port Control register provides access to all sub-registers that configure the GPIO Port operation.
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Port A-H Data Direction Sub-Registers The Port A-H Data Direction sub-register is accessed through the Port A-H Control register by writing 01H to the Port A-H Address register (Table 16).
Table 16. Port A-H Data Direction Sub-Registers
BITS FIELD RESET R/W ADDR
7
DD7
6
DD6
5
DD5
4
DD4 1 R/W
3
DD3
2
DD2
1
DD1
0
DD0
If 01H in Port A-H Address Register, accessible through Port A-H Control Register
DD[7:0]--Data Direction These bits control the direction of the associated port pin. Port Alternate Function operation overrides the Data Direction register setting. 0 = Output. Data in the Port A-H Output Data register is driven onto the port pin. 1 = Input. The port pin is sampled and the value written into the Port A-H Input Data Register. The output driver is tri-stated. Port A-H Alternate Function Sub-Registers The Port A-H Alternate Function sub-register (Table 17) is accessed through the Port A- H Control register by writing 02H to the Port A-H Address register. The Port A-H Alternate Function sub-registers select the alternate functions for the selected pins. Refer to the GPIO Alternate Functions section to determine the alternate function associated with each port pin. Caution: Do not enable alternate function for GPIO port pins which do not have an associated alternate function. Failure to follow this guideline may result in unpredictable operation.
Table 17. Port A-H Alternate Function Sub-Registers
BITS FIELD RESET R/W ADDR
7
AF7
6
AF6
5
AF5
4
AF4 0 R/W
3
AF3
2
AF2
1
AF1
0
AF0
If 02H in Port A-H Address Register, accessible through Port A-H Control Register
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AF[7:0]--Port Alternate Function enabled 0 = The port pin is in normal mode and the DDx bit in the Port A-H Data Direction subregister determines the direction of the pin. 1 = The alternate function is selected. Port pin operation is controlled by the alternate function. Port A-H Output Control Sub-Registers The Port A-H Output Control sub-register (Table 18) is accessed through the Port A-H Control register by writing 03H to the Port A-H Address register. Setting the bits in the Port A-H Output Control sub-registers to 1 configures the specified port pins for opendrain operation. These sub-registers affect the pins directly and, as a result, alternate functions are also affected.
Table 18. Port A-H Output Control Sub-Registers
BITS FIELD RESET R/W ADDR
7
POC7
6
POC6
5
POC5
4
POC4 0 R/W
3
POC3
2
POC2
1
POC1
0
POC0
If 03H in Port A-H Address Register, accessible through Port A-H Control Register
POC[7:0]--Port Output Control These bits function independently of the alternate function bit and disables the drains if set to 1. 0 = The drains are enabled for any output mode. 1 = The drain of the associated pin is disabled (open-drain mode).
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Port A-H High Drive Enable Sub-Registers The Port A-H High Drive Enable sub-register (Table 19) is accessed through the Port A- H Control register by writing 04H to the Port A-H Address register. Setting the bits in the Port A-H High Drive Enable sub-registers to 1 configures the specified port pins for high current output drive operation. The Port A-H High Drive Enable sub-register affects the pins directly and, as a result, alternate functions are also affected.
Table 19. Port A-H High Drive Enable Sub-Registers
BITS FIELD RESET R/W ADDR
7
PHDE7
6
PHDE6
5
PHDE5
4
PHDE4 0 R/W
3
PHDE3
2
PHDE2
1
PHDE1
0
PHDE0
If 04H in Port A-H Address Register, accessible through Port A-H Control Register
PHDE[7:0]--Port High Drive Enabled 0 = The Port pin is configured for standard output current drive. 1 = The Port pin is configured for high output current drive. Port A-H STOP Mode Recovery Source Enable Sub-Registers The Port A-H STOP Mode Recovery Source Enable sub-register (Table 20) is accessed through the Port A-H Control register by writing 05H to the Port A-H Address register. Setting the bits in the Port A-H STOP Mode Recovery Source Enable sub-registers to 1 configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode, any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates STOP Mode Recovery.
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Table 20. Port A-H STOP Mode Recovery Source Enable Sub-Registers
BITS FIELD RESET R/W ADDR
7
PSMRE7
6
PSMRE6
5
PSMRE5
4
PSMRE4 0 R/W
3
PSMRE3
2
PSMRE2
1
PSMRE1
0
PSMRE0
If 05H in Port A-H Address Register, accessible through Port A-H Control Register
PSMRE[7:0]--Port STOP Mode Recovery Source Enabled 0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this pin during STOP mode do not initiate STOP Mode Recovery. 1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on this pin during STOP mode initiates STOP Mode Recovery.
Port A-H Input Data Registers
Reading from the Port A-H Input Data registers (Table 21) returns the sampled values from the corresponding port pins. The Port A-H Input Data registers are Read-only.
Table 21. Port A-H Input Data Registers (PxIN)
BITS FIELD RESET R/W ADDR
7
PIN7
6
PIN6
5
PIN5
4
PIN4 X R
3
PIN3
2
PIN2
1
PIN1
0
PIN0
FD2H, FD6H, FDAH, FDEH, FE2H, FE6H, FEAH, FEEH
PIN[7:0]--Port Input Data Sampled data from the corresponding port pin input. 0 = Input data is logical 0 (Low). 1 = Input data is logical 1 (High).
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Port A-H Output Data Register
The Port A-H Output Data register (Table 22) writes output data to the pins.
Table 22. Port A-H Output Data Register (PxOUT)
BITS FIELD RESET R/W ADDR
7
POUT7
6
POUT6
5
POUT5
4
POUT4 0 R/W
3
POUT3
2
POUT2
1
POUT1
0
POUT0
FD3H, FD7H, FDBH, FDFH, FE3H, FE7H, FEBH, FEFH
POUT[7:0]--Port Output Data These bits contain the data to be driven out from the port pins. The values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = Drive a logical 0 (Low). 1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting the corresponding Port Output Control register bit to 1.
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Interrupt Controller
Overview
The interrupt controller on the 64K Series products prioritizes the interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the interrupt controller include the following:
*
24 unique interrupt vectors: - 12 GPIO port pin interrupt sources - 12 on-chip peripheral interrupt sources Flexible GPIO interrupts - 8 selectable rising and falling edge GPIO interrupts - 4 dual-edge interrupts 3 levels of individually programmable interrupt priority Watch-Dog Timer can be configured to generate an interrupt
*
* *
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt service routine is involved with the exchange of data, status information, or control information between the CPU and the interrupting peripheral. When the service routine is completed, the CPU returns to the operation from which it was interrupted. The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt control has no effect on operation. Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Manual is available for download at www.zilog.com.
Interrupt Vector Listing
Table 23 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most significant byte (MSB) at the even Program Memory address and the least significant byte (LSB) at the following odd Program Memory address.
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Table 23. Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt Source Highest 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H Lowest 0036H Reset (not an interrupt) Watch-Dog Timer (see Watch-Dog Timer chapter) Illegal Instruction Trap (not an interrupt) Timer 2 Timer 1 Timer 0 UART 0 receiver UART 0 transmitter I2C SPI ADC Port A7 or Port D7, rising or falling input edge Port A6 or Port D6, rising or falling input edge Port A5 or Port D5, rising or falling input edge Port A4 or Port D4, rising or falling input edge Port A3 or Port D3, rising or falling input edge Port A2 or Port D2, rising or falling input edge Port A1 or Port D1, rising or falling input edge Port A0 or Port D0, rising or falling input edge Timer 3 (not available in 44-pin packages) UART 1 receiver UART 1 transmitter DMA Port C3, both input edges Port C2, both input edges Port C1, both input edges Port C0, both input edges
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Architecture
Figure 11 illustrates a block diagram of the interrupt controller.
Port Interrupts Interrupt Request Latches and Control
High Priority Vector Priority Mux IRQ Request
Medium Priority
Internal Interrupts
Low Priority
Figure 11. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions:
* * * * * * *
Executing an EI (Enable Interrupt) instruction Executing an IRET (Return from Interrupt) instruction Writing a 1 to the IRQE bit in the Interrupt Control register Execution of a DI (Disable Interrupt) instruction eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller Writing a 0 to the IRQE bit in the Interrupt Control register Reset
Interrupts are globally disabled by any of the following actions:
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* *
Executing a Trap instruction Illegal Instruction trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of the interrupts were enabled with identical interrupt priority (all as Level 2 interrupts, for example), then interrupt priority would be assigned from highest to lowest as specified in Table 23. Level 3 interrupts always have higher priority than Level 2 interrupts which, in turn, always have higher priority than Level 1 interrupts. Within each interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 23. Reset, Watch-Dog Timer interrupt (if enabled), and Illegal Instruction Trap always have highest priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the corresponding bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a 0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt request. Caution: The following style of coding to clear bits in the Interrupt Request registers is NOT recommended. All incoming interrupts that are received between execution of the first LDX command and the last LDX command are lost. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 AND r0, MASK LDX IRQ0, r0 To avoid missing interrupts, the following style of coding to clear bits in the Interrupt Request 0 register is recommended: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the desired bit in the Interrupt Request register triggers an interrupt (assuming that interrupt is enabled). When the interrupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is automatically cleared to 0.
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Caution:
The following style of coding to generate software interrupts by setting bits in the Interrupt Request registers is NOT recommended. All incoming interrupts that are received between execution of the first LDX command and the last LDX command are lost. Poor coding style that can result in lost interrupt requests: LDX r0, IRQ0 OR r0, MASK LDX IRQ0, r0 To avoid missing interrupts, the following style of coding to set bits in the Interrupt Request registers is recommended: Good coding style that avoids lost interrupt requests: ORX IRQ0, MASK
Interrupt Control Register Definitions
For all interrupts other than the Watch-Dog Timer interrupt, the interrupt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 24) stores the interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 0 register to determine if any interrupt requests are pending
Table 24. Interrupt Request 0 Register (IRQ0)
BITS FIELD RESET R/W ADDR
7
T2I
6
T1I
5
T0I
4
U0RXI 0 R/W FC0H
3
U0TXI
2
I2CI
1
SPII
0
ADCI
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T2I--Timer 2 Interrupt Request 0 = No interrupt request is pending for Timer 2. 1 = An interrupt request from Timer 2 is awaiting service. T1I--Timer 1 Interrupt Request 0 = No interrupt request is pending for Timer 1. 1 = An interrupt request from Timer 1 is awaiting service. T0I--Timer 0 Interrupt Request 0 = No interrupt request is pending for Timer 0. 1 = An interrupt request from Timer 0 is awaiting service. U0RXI--UART 0 Receiver Interrupt Request 0 = No interrupt request is pending for the UART 0 receiver. 1 = An interrupt request from the UART 0 receiver is awaiting service. U0TXI--UART 0 Transmitter Interrupt Request 0 = No interrupt request is pending for the UART 0 transmitter. 1 = An interrupt request from the UART 0 transmitter is awaiting service. I2CI-- I2C Interrupt Request 0 = No interrupt request is pending for the I2C. 1 = An interrupt request from the I2C is awaiting service. SPII--SPI Interrupt Request 0 = No interrupt request is pending for the SPI. 1 = An interrupt request from the SPI is awaiting service. ADCI--ADC Interrupt Request 0 = No interrupt request is pending for the Analog-to-Digital Converter. 1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 25) stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending.
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Table 25. Interrupt Request 1 Register (IRQ1)
BITS FIELD RESET R/W ADDR
7
PAD7I
6
PAD6I
5
PAD5I
4
PAD4I 0 R/W FC3H
3
PAD3I
2
PAD2I
1
PAD1I
0
PAD0I
PADxI--Port A or Port D Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port A or Port D pin x. 1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service. where x indicates the specific GPIO Port pin number (0 through 7). For each pin, only 1 of either Port A or Port D can be enabled for interrupts at any one time. Port selection (A or D) is determined by the values in the Interrupt Port Select Register.
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 26) stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending.
Table 26. Interrupt Request 2 Register (IRQ2)
BITS FIELD RESET R/W ADDR
7
T3I
6
U1RXI
5
U1TXI
4
DMAI 0 R/W FC6H
3
PC3I
2
PC2I
1
PC1I
0
PC0I
T3I--Timer 3 Interrupt Request 0 = No interrupt request is pending for Timer 3. 1 = An interrupt request from Timer 3 is awaiting service.
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U1RXI--UART 1 Receive Interrupt Request 0 = No interrupt request is pending for the UART1 receiver. 1 = An interrupt request from UART1 receiver is awaiting service. U1TXI--UART 1 Transmit Interrupt Request 0 = No interrupt request is pending for the UART 1 transmitter. 1 = An interrupt request from the UART 1 transmitter is awaiting service. DMAI--DMA Interrupt Request 0 = No interrupt request is pending for the DMA. 1 = An interrupt request from the DMA is awaiting service. PCxI--Port C Pin x Interrupt Request 0 = No interrupt request is pending for GPIO Port C pin x. 1 = An interrupt request from GPIO Port C pin x is awaiting service. where x indicates the specific GPIO Port C pin number (0 through 3).
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers (Tables 28 and 29) form a priority encoded enabling for interrupts in the Interrupt Request 0 register. Priority is generated by setting bits in each register. Table 27 describes the priority control for IRQ0.
Table 27. IRQ0 Enable and Priority Encoding IRQ0ENH[x] IRQ0ENL[x] Priority 0 0 1 1 0 1 0 1 Disabled Level 1 Level 2 Level 3 Description Disabled Low Nominal High
where x indicates the register bits from 0 through 7.
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS FIELD RESET R/W ADDR
7
T2ENH
6
T1ENH
5
T0ENH
4
U0RENH 0 R/W FC1H
3
U0TENH
2
I2CENH
1
SPIENH
0
ADCENH
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T2ENH--Timer 2 Interrupt Request Enable High Bit T1ENH--Timer 1 Interrupt Request Enable High Bit T0ENH--Timer 0 Interrupt Request Enable High Bit U0RENH--UART 0 Receive Interrupt Request Enable High Bit U0TENH--UART 0 Transmit Interrupt Request Enable High Bit I2CENH--I2C Interrupt Request Enable High Bit SPIENH--SPI Interrupt Request Enable High Bit ADCENH--ADC Interrupt Request Enable High Bit
Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS FIELD RESET R/W ADDR
7
T2ENL
6
T1ENL
5
T0ENL
4
U0RENL 0 R/W FC2H
3
U0TENL
2
I2CENL
1
SPIENL
0
ADCENL
T2ENL--Timer 2 Interrupt Request Enable Low Bit T1ENL--Timer 1 Interrupt Request Enable Low Bit T0ENL--Timer 0 Interrupt Request Enable Low Bit U0RENL--UART 0 Receive Interrupt Request Enable Low Bit U0TENL--UART 0 Transmit Interrupt Request Enable Low Bit I2CENL--I2C Interrupt Request Enable Low Bit SPIENL--SPI Interrupt Request Enable Low Bit ADCENL--ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers (Tables 31 and 32) form a priority encoded enabling for interrupts in the Interrupt Request 1 register. Priority is generated by setting bits in each register. Table 30 describes the priority control for IRQ1.
Table 30. IRQ1 Enable and Priority Encoding IRQ1ENH[x] IRQ1ENL[x] Priority 0 0 1 1 0 1 0 1 Disabled Level 1 Level 2 Level 3 Description Disabled Low Nominal High
where x indicates the register bits from 0 through 7.
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Table 31. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
7
6
5
4
3
2
1
0
FIELD PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH RESET R/W ADDR
0 R/W 0 R/W 0 R/W 0 R/W FC4H 0 R/W 0 R/W 0 R/W 0 R/W
PADxENH--Port A or Port D Bit[x] Interrupt Request Enable High Bit Refer to the Interrupt Port Select register for selection of either Port A or Port D as the interrupt source.
Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS FIELD RESET R/W ADDR
7
6
5
4
3
2
1
0
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL 0 R/W 0 R/W 0 R/W 0 R/W FC5H 0 R/W 0 R/W 0 R/W 0 R/W
PADxENL--Port A or Port D Bit[x] Interrupt Request Enable Low Bit Refer to the Interrupt Port Select register for selection of either Port A or Port D as the interrupt source.
IRQ2 Enable High and Low Bit Registers
The IRQ2 Enable High and Low Bit registers (Tables 34 and 35) form a priority encoded enabling for interrupts in the Interrupt Request 2 register. Priority is generated by setting bits in each register. Table 33 describes the priority control for IRQ2.
Table 33. IRQ2 Enable and Priority Encoding IRQ2ENH[x] IRQ2ENL[x] Priority 0 0 1 1 0 1 0 1 Disabled Level 1 Level 2 Level 3 Description Disabled Low Nominal High
where x indicates the register bits from 0 through 7.
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Table 34. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS FIELD RESET R/W ADDR
7
T3ENH
6
U1RENH
5
U1TENH
4
DMAENH 0 R/W FC7H
3
C3ENH
2
C2ENH
1
C1ENH
0
C0ENH
T3ENH--Timer 3 Interrupt Request Enable High Bit U1RENH--UART 1 Receive Interrupt Request Enable High Bit U1TENH--UART 1 Transmit Interrupt Request Enable High Bit DMAENH--DMA Interrupt Request Enable High Bit C3ENH--Port C3 Interrupt Request Enable High Bit C2ENH--Port C2 Interrupt Request Enable High Bit C1ENH--Port C1 Interrupt Request Enable High Bit C0ENH--Port C0 Interrupt Request Enable High Bit
Table 35. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS FIELD RESET R/W ADDR
7
T3ENL
6
U1RENL
5
U1TENL
4
DMAENL 0 R/W FC8H
3
C3ENL
2
C2ENL
1
C1ENL
0
C0ENL
T3ENL--Timer 3 Interrupt Request Enable Low Bit U1RENL--UART 1 Receive Interrupt Request Enable Low Bit U1TENL--UART 1 Transmit Interrupt Request Enable Low Bit DMAENL--DMA Interrupt Request Enable Low Bit C3ENL--Port C3 Interrupt Request Enable Low Bit C2ENL--Port C2 Interrupt Request Enable Low Bit C1ENL--Port C1 Interrupt Request Enable Low Bit C0ENL--Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 36) determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port input pin. The
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Interrupt Port Select register selects between Port A and Port D for the individual interrupts.
Table 36. Interrupt Edge Select Register (IRQES)
BITS FIELD RESET R/W ADDR
7
IES7
6
IES6
5
IES5
4
IES4 0 R/W FCDH
3
IES3
2
IES2
1
IES1
0
IES0
IESx--Interrupt Edge Select x The minimum pulse width should be greater than 1 system clock to guarantee capture of the edge triggered interrupt. Shorter pulses may be captured but not guaranteed. 0 = An interrupt request is generated on the falling edge of the PAx/PDx input. 1 = An interrupt request is generated on the rising edge of the PAx/PDx input. where x indicates the specific GPIO Port pin number (0 through 7),
Interrupt Port Select Register
The Port Select (IRQPS) register (Table 37) determines the port pin that generates the PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as interrupts. The Interrupt Edge Select register controls the active interrupt edge.
Table 37. Interrupt Port Select Register (IRQPS)
BITS FIELD RESET R/W ADDR
7
PAD7S
6
PAD6S
5
PAD5S
4
PAD4S 0 R/W
3
PAD3S
2
PAD2S
1
PAD1S
0
PAD0S
FCEH PADxS--PAx/PDx Selection 0 = PAx is used for the interrupt for PAx/PDx interrupt request. 1 = PDx is used for the interrupt for PAx/PDx interrupt request. where x indicates the specific GPIO Port pin number (0 through 7)
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Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 38) contains the master enable bit for all interrupts.
Table 38. Interrupt Control Register (IRQCTL)
BITS FIELD RESET R/W ADDR
7
IRQE
6
5
4
3
Reserved 0
2
1
0
R/W FCFH
R
IRQE--Interrupt Request Enable This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return) instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of an interrupt request, or Reset. 0 = Interrupts are disabled 1 = Interrupts are enabled Reserved Must be 0.
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Timers
Overview
The 64K Series products contain up to four 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (PWM) signals. The timers' features include:
* * * * * * *
16-bit reload counter Programmable prescaler with prescale values from 1 to 128 PWM output generation Capture and compare capability External input pin for timer input, clock gating, or capture signal. External input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. Timer output pin Timer interrupt
In addition to the timers described in this chapter, the Baud Rate Generators for any unused UART, SPI, or I2C peripherals may also be used to provide basic timing functionality. Refer to the respective serial communication peripheral chapters for information on using the Baud Rate Generators as timers. Timer 3 is unavailable in the 44-pin package devices.
Architecture
Figure 12 illustrates the architecture of the timers.
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Timer Block Data Bus Block Control Timer Control
Compare
16-Bit Reload Register
System Clock Timer Input Gate Input Capture Input
Interrupt, PWM, and Timer Output Control
Timer Interrupt Timer Output
16-Bit Counter with Prescaler Compare
16-Bit PWM / Compare
Figure 12. Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value 0001H into the Timer Reload High and Low Byte registers and setting the prescale value to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload High and Low Byte registers and setting the prescale value to 128. If the Timer reaches FFFFH, the timer rolls over to 0000H and continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes: ONE-SHOT Mode In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt and the count value in the Timer High and Low Byte registers is reset to 0001H. Then, the timer is automatically disabled and stops counting. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If it is desired to have the Timer Output make a permanent state change upon One-Shot time-
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out, first set the TPOL bit in the Timer Control 1 Register to the start value before beginning ONE-SHOT mode. Then, after starting the timer, set TPOL to the opposite bit value. The steps for configuring a timer for ONE-SHOT mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: - Disable the timer - Configure the timer for ONE-SHOT mode - Set the prescale value - If using the Timer Output alternate function, set the initial output level (High or Low) 2. Write to the Timer High and Low Byte registers to set the starting count value 3. Write to the Timer Reload High and Low Byte registers to set the Reload value 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function 6. Write to the Timer Control 1 register to enable the timer and initiate counting In ONE-SHOT mode, the system clock always provides the timer input. The timer period is given by the following equation: ( Reload Value Start Value ) x Prescale One-Shot Mode Time-Out Period (s) = ------------------------------------------------------------------------------------------------------System Clock Frequency (Hz) CONTINUOUS Mode In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon timer Reload. The steps for configuring a timer for CONTINUOUS mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: - Disable the timer - Configure the timer for CONTINUOUS mode - Set the prescale value
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-
If using the Timer Output alternate function, set the initial output level (High or Low)
2. Write to the Timer High and Low Byte registers to set the starting count value (usually 0001H), affecting only the first pass in CONTINUOUS mode. After the first timer Reload in CONTINUOUS mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control 1 register to enable the timer and initiate counting. In CONTINUOUS mode, the system clock always provides the timer input. The timer period is given by the following equation: Reload Value x Prescale Continuous Mode Time-Out Period (s) = --------------------------------------------------------------------------System Clock Frequency (Hz) If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the ONE-SHOT mode equation must be used to determine the first time-out period. COUNTER Mode In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the Timer Control 1 Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled. Caution: The input frequency of the Timer Input signal must not exceed one-fourth the system clock frequency.
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. The steps for configuring a timer for COUNTER mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: - Disable the timer - Configure the timer for COUNTER mode
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-
Select either the rising edge or falling edge of the Timer Input signal for the count. This also sets the initial logic level (High or Low) for the Timer Output alternate function. However, the Timer Output function does not have to be enabled
2. Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in COUNTER mode. After the first timer Reload in COUNTER mode, counting always begins at the reset value of 0001H. Generally, in COUNTER mode the Timer High and Low Byte registers must be written with the value 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pin for the Timer Input alternate function. 6. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control 1 register to enable the timer. In COUNTER mode, the number of Timer Input transitions since the timer start is given by the following equation: Counter Mode Timer Input Transitions = Current Count Value Start Value
PWM Mode In PWM mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16bit PWM match value stored in the Timer PWM High and Low Byte registers. When the timer count value matches the PWM value, the Timer Output toggles. The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. If the TPOL bit in the Timer Control 1 register is set to 1, the Timer Output signal begins as a High (1) and then transitions to a Low (0) when the timer value matches the PWM value. The Timer Output signal returns to a High (1) after the timer reaches the Reload value and is reset to 0001H. If the TPOL bit in the Timer Control 1 register is set to 0, the Timer Output signal begins as a Low (0) and then transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is reset to 0001H. The steps for configuring a timer for PWM mode and initiating the PWM operation are as follows:
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1. Write to the Timer Control 1 register to: - Disable the timer - Configure the timer for PWM mode - Set the prescale value - Set the initial logic level (High or Low) and PWM High/Low transition for the Timer Output alternate function 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). This only affects the first pass in PWM mode. After the first timer reset in PWM mode, counting always begins at the reset value of 0001H. 3. Write to the PWM High and Low Byte registers to set the PWM value. 4. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM period). The Reload value must be greater than the PWM value. 5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pin for the Timer Output alternate function. 7. Write to the Timer Control 1 register to enable the timer and initiate counting. The PWM period is given by the following equation: Reload Value x Prescale PWM Period (s) = --------------------------------------------------------------------------System Clock Frequency (Hz) If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers, the One-Shot mode equation must be used to determine the first PWM time-out period. If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by: Reload Value PWM Value PWM Output High Time Ratio (%) = ------------------------------------------------------------------------- x 100 Reload Value If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by: PWM Value PWM Output High Time Ratio (%) = --------------------------------- x 100 Reload Value Capture Mode In CAPTURE mode, the current timer count value is recorded when the desired external Timer Input transition occurs. The Capture count value is written to the Timer PWM High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer Control 1 register determines if the Capture occurs on a rising edge or a falling edge of the
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Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer continues counting. The timer continues counting up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt and continues counting. The steps for configuring a timer for CAPTURE mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: - Disable the timer - Configure the timer for CAPTURE mode. - Set the prescale value. - Set the Capture edge (rising or falling) for the Timer Input. 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H). 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user software to determine if interrupts were generated by either a capture event or a reload. If the PWM High and Low Byte registers still contain 0000H after the interrupt, then the interrupt was generated by a Reload. 5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 6. Configure the associated GPIO port pin for the Timer Input alternate function. 7. Write to the Timer Control 1 register to enable the timer and initiate counting. In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: ( Capture Value Start Value ) x Prescale Capture Elapsed Time (s) = ---------------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
Compare Mode In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon reaching the Compare value, the timer generates an interrupt and counting continues (the timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) upon Compare.
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If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting. The steps for configuring a timer for COMPARE mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: - Disable the timer - Configure the timer for COMPARE mode - Set the prescale value - Set the initial logic level (High or Low) for the Timer Output alternate function, if desired 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. If using the Timer Output function, configure the associated GPIO port pin for the Timer Output alternate function. 6. Write to the Timer Control 1 register to enable the timer and initiate counting. In COMPARE mode, the system clock always provides the timer input. The Compare time is given by the following equation: ( Compare Value Start Value ) x Prescale Compare Mode Time (s) = ------------------------------------------------------------------------------------------------------------System Clock Frequency (Hz) GATED Mode In GATED mode, the timer counts only when the Timer Input signal is in its active state (asserted), as determined by the TPOL bit in the Timer Control 1 register. When the Timer Input signal is asserted, counting begins. A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal deassertion generated the interrupt, read the associated GPIO input value and compare to the value stored in the TPOL bit. The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low Byte registers. The timer input is the system clock. When reaching the Reload value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes (assuming the Timer Input signal is still asserted). Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state (from Low to High or from High to Low) at timer reset.
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The steps for configuring a timer for GATED mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: - Disable the timer - Configure the timer for GATED mode - Set the prescale value 2. Write to the Timer High and Low Byte registers to set the starting count value. This only affects the first pass in GATED mode. After the first timer reset in GATED mode, counting always begins at the reset value of 0001H. 3. Write to the Timer Reload High and Low Byte registers to set the Reload value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pin for the Timer Input alternate function. 6. Write to the Timer Control 1 register to enable the timer. 7. Assert the Timer Input signal to initiate the counting. CAPTURE/COMPARE Mode In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer Input transition. The desired transition (rising edge or falling edge) is set by the TPOL bit in the Timer Control 1 Register. The timer input is the system clock. Every subsequent desired transition (after the first) of the Timer Input signal captures the current count value. The Capture value is written to the Timer PWM High and Low Byte Registers. When the Capture event occurs, an interrupt is generated, the count value in the Timer High and Low Byte registers is reset to 0001H, and counting resumes. If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer generates an interrupt, the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes. The steps for configuring a timer for CAPTURE/COMPARE mode and initiating the count are as follows: 1. Write to the Timer Control 1 register to: - Disable the timer - Configure the timer for CAPTURE/COMPARE mode - Set the prescale value - Set the Capture edge (rising or falling) for the Timer Input 2. Write to the Timer High and Low Byte registers to set the starting count value (typically 0001H).
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3. Write to the Timer Reload High and Low Byte registers to set the Compare value. 4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers. 5. Configure the associated GPIO port pin for the Timer Input alternate function. 6. Write to the Timer Control 1 register to enable the timer. 7. Counting begins on the first appropriate transition of the Timer Input signal. No interrupt is generated by this first edge. In m/COMPARE mode, the elapsed time from timer start to Capture event can be calculated using the following equation: ( Capture Value Start Value ) x Prescale Capture Elapsed Time (s) = ---------------------------------------------------------------------------------------------------------System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability has no effect on timer operation. When the timer is enabled and the Timer High Byte register is read, the contents of the Timer Low Byte register are placed in a holding register. A subsequent read from the Timer Low Byte register returns the value in the holding register. This operation allows accurate reads of the full 16-bit timer count value while enabled. When the timers are not enabled, a read from the Timer Low Byte register returns the actual value in the counter.
Timer Output Signal Operation
Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is toggled every time the counter is reloaded.
Timer Control Register Definitions
Timers 0-2 are available in all packages. Timer 3 is only available in the 64-, 68-, and 80pin packages.
Timer 0-3 High and Low Byte Registers
The Timer 0-3 High and Low Byte (TxH and TxL) registers (Tables 38 and 39) contain the current 16-bit timer count value. When the timer is enabled, a read from TxH causes the value in TxL to be stored in a temporary holding register. A read from TMRL always returns this temporary register when the timers are enabled. When the timer is disabled, reads from the TMRL reads the register directly. Writing to the Timer High and Low Byte registers while the timer is enabled is not recommended. There are no temporary holding registers available for write operations, so simul-
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taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are written during counting, the 8-bit written value is placed in the counter (High or Low Byte) at the next clock edge. The counter continues counting from the new value. Timer 3 is unavailable in the 40- and 44-pin packages.
Table 38. Timer 0-3 High Byte Register (TxH)
BITS FIELD RESET R/W ADDR
7
6
5
4
TH 0 R/W
3
2
1
0
F00H, F08H, F10H, F18H
Table 39>. Timer 0-3 Low Byte Register (TxL)
BITS FIELD RESET R/W ADDR
7
6
5
4
TL 0 R/W
3
2
1
0
1
F01H, F09H, F11H, F19H
TH and TL--Timer High and Low Bytes These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0-3 Reload High and Low Byte (TxRH and TxRL) registers (Tables 40 and 41) store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte register are stored in a temporary holding register. When a write to the Timer Reload Low Byte register occurs, the temporary holding register value is written to the Timer High Byte register. This operation allows simultaneous updates of the 16-bit Timer Reload value. In COMPARE mode, the Timer Reload High and Low Byte registers store the 16-bit Compare value.
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Table 40. Timer 0-3 Reload High Byte Register (TxRH)
BITS FIELD RESET R/W ADDR
7
6
5
4
TRH 1 R/W
3
2
1
0
F02H, F0AH, F12H, F1AH
Table 41. Timer 0-3 Reload Low Byte Register (TxRL)
BITS FIELD RESET R/W ADDR
7
6
5
4
TRL 1 R/W
3
2
1
0
F03H, F0BH, F13H, F1BH
TRH and TRL--Timer Reload Register High and Low These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the maximum count value which initiates a timer reload to 0001H. In COMPARE mode, these two byte form the 16-bit Compare value.
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Timer 0-3 PWM High and Low Byte Registers
The Timer 0-3 PWM High and Low Byte (TxPWMH and TxPWML) registers (Tables 42 and 43) are used for Pulse-Width Modulator (PWM) operations. These registers also store the Capture values for the Capture and Capture/COMPARE modes.
Table 42. Timer 0-3 PWM High Byte Register (TxPWMH)
BITS FIELD RESET R/W ADDR
7
6
5
4
PWMH 0 R/W
3
2
1
0
F04H, F0CH, F14H, F1CH
Table 43. Timer 0-3 PWM Low Byte Register (TxPWML)
BITS FIELD RESET R/W ADDR
7
6
5
4
PWML 0 R/W
3
2
1
0
F05H, F0DH, F15H, F1DH
PWMH and PWML--Pulse-Width Modulator High and Low Bytes These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. When a match occurs, the PWM output changes state. The PWM output value is set by the TPOL bit in the Timer Control 1 Register (TxCTL1) register. The TxPWMH and TxPWML registers also store the 16-bit captured timer value when operating in Capture or Capture/COMPARE modes.
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Timer 0-3 Control 0 Registers
The Timer 0-3 Control 0 (TxCTL0) registers (Tables 44 and 45) allow cascading of the Timers.
Table 44. Timer 0-3 Control 0 Register (TxCTL0)
BITS FIELD RESET R/W ADDR
7
6
Reserved
5
4
CSC 0 R/W
3
2
Reserved
1
0
F06H, F0EH, F16H, F1EH
CSC--Cascade Timers 0 = Timer Input signal comes from the pin. 1 = For Timer 0, Input signal is connected to Timer 3 output. For Timer 1, Input signal is connected to Timer 0 output. For Timer 2, Input signal is connected to Timer 1 output. For Timer 3, Input signal is connected to Timer 2 output.
Timer 0-3 Control 1 Registers
The Timer 0-3 Control 1 (TxCTL1) registers enable/disable the timers, set the prescaler value, and determine the timer operating mode.
Table 45. Timer 0-3 Control 1 Register (TxCTL1)
BITS FIELD RESET R/W ADDR
7
TEN
6
TPOL
5
4
PRES 0 R/W
3
2
1
TMODE
0
F07H, F0FH, F17H, F1FH
TEN--Timer Enable 0 = Timer is disabled. 1 = Timer enabled to count. TPOL--Timer Input/Output Polarity Operation of this bit is a function of the current operating mode of the timer.
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ONE-SHOT mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. CONTINUOUS mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. COUNTER mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. PWM mode 0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload. 1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count match and forced High (1) upon Reload. CAPTURE mode 0 = Count is captured on the rising edge of the Timer Input signal. 1 = Count is captured on the falling edge of the Timer Input signal. COMPARE mode When the timer is disabled, the Timer Output signal is set to the value of this bit. When the timer is enabled, the Timer Output signal is complemented upon timer Reload. GATED mode 0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the falling edge of the Timer Input. 1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the rising edge of the Timer Input. CAPTURE/COMPARE mode 0 = Counting is started on the first rising edge of the Timer Input signal. The current count is captured on subsequent rising edges of the Timer Input signal. 1 = Counting is started on the first falling edge of the Timer Input signal. The current count is captured on subsequent falling edges of the Timer Input signal.
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Caution:
When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, TxOUT will change to whatever state the TPOL bit is in. The timer does not need to be enabled for that to happen. Also, the Port data direction sub register is not needed to be set to output on TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately change the TxOUT. PRES--Prescale value. The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The prescaler is reset each time the Timer is disabled. This insures proper clock division each time the Timer is restarted. 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Divide by 128 TMODE--TIMER mode 000 = ONE-SHOT mode 001 = CONTINUOUS mode 010 = COUNTER mode 011 = PWM mode 100 = CAPTURE mode 101 = COMPARE mode 110 = GATED mode 111 = CAPTURE/COMPARe mode
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Watch-Dog Timer
Overview
The Watch-Dog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which may place the Z8 Encore!(R) into unsuitable operating states. The Watch-Dog Timer includes the following features:
* * * * Operation
On-chip RC oscillator A selectable time-out response: WDT Time-out response: Reset or interrupt 24-bit programmable time-out value
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the 64K Series devices when the WDT reaches its terminal count. The Watch-Dog Timer uses its own dedicated on-chip RC oscillator as its clock source. The Watch-Dog Timer has only two modes of operation--ON and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out. An enable can be performed by executing the WDT instruction or by setting the WDT_AO Option Bit. The WDT_AO bit enables the Watch-Dog Timer to operate all the time, even if a WDT instruction has not been executed. The Watch-Dog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is given by the following equation:
WDT Reload Value WDT Time-out Period (ms) = ------------------------------------------------10
where the WDT reload value is the decimal value of the 24-bit value given by {WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watch-Dog Timer RC oscillator frequency is 10kHz. The Watch-Dog Timer cannot be refreshed once it reaches 000002H. The WDT Reload Value must not be set to values below 000004H. Table 46 provides information on approximate time-out delays for the minimum and maximum WDT reload values.
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Table 46. Watch-Dog Timer Approximate Time-Out Delays Approximate Time-Out Delay (with 10kHz typical WDT oscillator frequency) Typical 400s 1677.5s Description Minimum time-out delay Maximum time-out delay
WDT Reload Value (Hex) 000004 FFFFFF
WDT Reload Value (Decimal) 4 16,777,215
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog Timer Reload registers. The Watch-Dog Timer then counts down to 000000H unless a WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer Reload registers. Counting resumes following the reload operation. When the 64K Series devices are operating in Debug Mode (through the On-Chip Debugger), the Watch-Dog Timer is continuously refreshed to prevent spurious Watch-Dog Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the Watch-Dog Timer generates either an interrupt or a Reset. The WDT_RES Option Bit determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits chapter for information regarding programming of the WDT_RES Option Bit. WDT Interrupt in Normal Operation If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Watch-Dog Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. After time-out and interrupt generation, the Watch-Dog Timer counter rolls over to its maximum value of FFFFFH and continues counting. The Watch-Dog Timer counter is not automatically returned to its Reload Value. WDT Interrupt in STOP Mode If configured to generate an interrupt when a time-out occurs and the 64K Series devices are in STOP mode, the Watch-Dog Timer automatically initiates a STOP Mode Recovery and generates an interrupt request. Both the WDT status bit and the STOP bit in the WatchDog Timer Control register are set to 1 following WDT time-out in STOP mode. Refer to
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the Reset and STOP Mode Recovery chapter for more information on STOP Mode Recovery. If interrupts are enabled, following completion of the STOP Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and executing code from the vector address. WDT Reset in Normal Operation If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the device into the Reset state. The WDT status bit in the Watch-Dog Timer Control register is set to 1. Refer to the Reset and STOP Mode Recovery chapter for more information on Reset. WDT Reset in STOP Mode If enabled in STOP mode and configured to generate a Reset when a time-out occurs and the device is in STOP mode, the Watch-Dog Timer initiates a STOP Mode Recovery. Both the WDT status bit and the STOP bit in the Watch-Dog Timer Control register are set to 1 following WDT time-out in STOP mode. Refer to the Reset and STOP Mode Recovery chapter for more information. Default operation is for the WDT and its RC oscillator to be enabled during STOP mode. WDT RC Disable in STOP Mode To minimize power consumption in STOP Mode, the WDT and its RC oscillator can be disabled in STOP mode. The following sequence configures the WDT to be disabled when the 64K Series devices enter STOP Mode following execution of a STOP instruction: 1. Write 55H to the Watch-Dog Timer Control register (WDTCTL). 2. Write AAH to the Watch-Dog Timer Control register (WDTCTL). 3. Write 81H to the Watch-Dog Timer Control register (WDTCTL) to configure the WDT and its oscillator to be disabled during STOP Mode. Alternatively, write 00H to the Watch-Dog Timer Control register (WDTCTL) as the third step in this sequence to reconfigure the WDT and its oscillator to be enabled during STOP Mode. This sequence only affects WDT operation in STOP mode.
Watch-Dog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watch-Dog Timer (WDTCTL) Control register address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers. The follow sequence is required to unlock the Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write access.
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1. Write 55H to the Watch-Dog Timer Control register (WDTCTL). 2. Write AAH to the Watch-Dog Timer Control register (WDTCTL). 3. Write the Watch-Dog Timer Reload Upper Byte register (WDTU). 4. Write the Watch-Dog Timer Reload High Byte register (WDTH). 5. Write the Watch-Dog Timer Reload Low Byte register (WDTL). All steps of the Watch-Dog Timer Reload Unlock sequence must be written in the order just listed. There must be no other register writes between each of these operations. If a register write occurs, the lock state machine resets and no further writes can occur, unless the sequence is restarted. The value in the Watch-Dog Timer Reload registers is loaded into the counter when the Watch-Dog Timer is first enabled and every time a WDT instruction is executed.
Watch-Dog Timer Control Register Definitions
Watch-Dog Timer Control Register
The Watch-Dog Timer Control (WDTCTL) register, detailed in Table 47, is a Read-Only register that indicates the source of the most recent Reset event, indicates a STOP Mode Recovery event, and indicates a Watch-Dog Timer time-out. Reading this register resets the upper four bits to 0. Writing the 55H, AAH unlock sequence to the Watch-Dog Timer Control (WDTCTL) register address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes to the time-out period. These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious writes to the Reload registers.
Table 47. Watch-Dog Timer Control Register (WDTCTL)
BITS FIELD RESET R/W ADDR
7
POR
6
STOP
5
WDT
4
EXT
3
2
Reserved 0
1
0
SM
See descriptions below R FF0H
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Reset or STOP Mode Recovery Event Power-On Reset Reset using RESET pin assertion Reset using Watch-Dog Timer time-out Reset using the On-Chip Debugger (OCDCTL[1] set to 1) Reset from STOP Mode using DBG Pin driven Low STOP Mode Recovery using GPIO pin transition STOP Mode Recovery using Watch-Dog Timer time-out 1 0 0 1 1 0 0
POR
STOP 0 0 0 0 0 1 1 0 0 1 0 0 0 1
WDT 0 1 0 0 0 0 0
EXT
POR--Power-On Reset Indicator If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT timeout or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read. STOP--STOP Mode Recovery Indicator If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both set to 1, the STOP Mode Recovery occurred due to a WDT time-out. If the STOP bit is 1 and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP mode. Reading this register also resets this bit. WDT--Watch-Dog Timer Time-Out Indicator If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A STOP Mode Recovery from a change in an input pin also resets this bit. Reading this register resets this bit. EXT--External Reset Indicator If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On Reset or a STOP Mode Recovery from a change in an input pin resets this bit. Reading this register resets this bit. Reserved These bits are reserved and must be 0. SM--STOP Mode Configuration Indicator 0 = Watch-Dog Timer and its internal RC oscillator will continue to operate in STOP Mode. 1 = Watch-Dog Timer and its internal RC oscillator will be disabled in STOP Mode.
Watch-Dog Timer Reload Upper, High and Low Byte Registers
The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) registers (Tables 48 through 50) form the 24-bit reload value that is loaded into the WatchDog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the desired Reload Value. Reading from these registers returns the current Watch-Dog Timer count value.
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Caution:
The 24-bit WDT Reload Value must not be set to a value less than
000004H.
Table 48. Watch-Dog Timer Reload Upper Byte Register (WDTU)
BITS FIELD RESET R/W ADDR
7
6
5
4
WDTU 1 R/W* FF1H
3
2
1
0
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTU--WDT Reload Upper Byte Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
Table 49. Watch-Dog Timer Reload High Byte Register (WDTH)
BITS FIELD RESET R/W ADDR
7
6
5
4
WDTH 1 R/W* FF2H
3
2
1
0
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTH--WDT Reload High Byte Middle byte, Bits[15:8], of the 24-bit WDT reload value.
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Table 50. Watch-Dog Timer Reload Low Byte Register (WDTL)
BITS FIELD RESET R/W ADDR
7
6
5
4
WDTL 1 R/W* FF3H
3
2
1
0
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTL--WDT Reload Low Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.
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UART
Overview
The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include:
* * * * * * * * * * Architecture
8-bit asynchronous data transfer Selectable even- and odd-parity generation and checking Option of one or two Stop bits Separate transmit and receive interrupts Framing, parity, overrun and break detection Separate transmit and receive enables 16-bit Baud Rate Generator (BRG) Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes Baud Rate Generator timer mode Driver Enable output for external bus transceivers
The UART consists of three primary functional blocks: transmitter, receiver, and baud rate generator. The UART's transmitter and receiver function independently, but employ the same baud rate and data format. Figure 13 illustrates the UART architecture.
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Parity Checker Receiver Control with address compare RXD Receive Shifter
Receive Data Register
Control Registers
System Bus
Transmit Data Register
Status Register
Baud Rate Generator
TXD
Transmit Shift Register Transmitter Control Parity Generator
CTS DE
Figure 13. UART Block Diagram
Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit first. An even or odd parity bit can be optionally added to the data stream. Each character begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits. Figures 14 and 15 illustrates the asynchronous data format employed by the UART without parity and with parity, respectively.
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Data Field Idle State of Line 1 Start 0 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 lsb msb
Stop Bit(s)
1 2
Figure 14. UART Asynchronous Data Format without Parity
Data Field Idle State of Line 1 Start 0 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity lsb msb
Stop Bit(s)
1 2
Figure 15. UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Follow these steps to transmit data using the polled method of operation: 1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. If multiprocessor mode is desired, write to the UART Control 1 register to enable Multiprocessor (9-bit) mode functions. - Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR mode. 4. Write to the UART Control 0 register to: - Set the transmit enable bit (TEN) to enable the UART for data transmission - If parity is desired and MULTIPROCESSOR mode is not enabled, set the parity enable bit (PEN) and select either Even or Odd parity (PSEL).
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-
Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin.
5. Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit Data register becomes available to receive new data. 6. Write the UART Control 1 register to select the outgoing address bit. 7. Set the MULTIPROCESSOR Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. 8. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. 9. If desired and MULTIPROCESSOR mode is enabled, make any changes to the MULTIPROCESSOR Bit Transmitter (MPBT) value. 10. To transmit additional bytes, return to Step 5.
Transmitting Data using the Interrupt-Driven Method
The UART transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission. Follow these steps to configure the UART for interruptdriven data transmission: 1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the desired priority. 5. If MULTIPROCESSOR mode is desired, write to the UART Control 1 register to enable MULTIPROCESSOR (9-bit) mode functions. 6. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR mode 7. Write to the UART Control 0 register to: - Set the transmit enable bit (TEN) to enable the UART for data transmission - Enable parity, if desired and if multiprocessor mode is not enabled, and select either even or odd parity - Set or clear the CTSE bit to enable or disable control from the remote receiver via the CTS pin
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8. Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Write the UART Control 1 register to select the outgoing address bit: - Set the MULTIPROCESSOR Bit Transmitter (MPBT) if sending an address byte, clear it if sending a data byte. 2. Write the data byte to the UART Transmit Data register. The transmitter automatically transfers the data to the Transmit Shift register and transmits the data. 3. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register. 4. Execute the IRET instruction to return from the interrupt-service routine and wait for the Transmit Data register to again become empty.
Receiving Data using the Polled Method
Follow these steps to configure the UART for polled data reception: 1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. Write to the UART Control 1 register to enable Multiprocessor mode functions, if desired. 4. Write to the UART Control 0 register to: - Set the receive enable bit (REN) to enable the UART for data reception - Enable parity, if desired and if multiprocessor mode is not enabled, and select either even or odd parity 5. Check the RDA bit in the UART Status 0 register to determine if the Receive Data register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate available data, continue to Step 6. If the Receive Data register is empty (indicated by a 0), continue to monitor the RDA bit awaiting reception of the valid data. 6. Read data from the UART Receive Data register. If operating in Multiprocessor (9-bit) mode, further actions may be required depending on the Multiprocessor Mode bits MPMD[1:0]. 7. Return to Step 5 to receive additional data.
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Receiving Data using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow these steps to configure the UART receiver for interrupt-driven operation: 1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate. 2. Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation. 3. Execute a DI instruction to disable interrupts. 4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set the desired priority. 5. Clear the UART Receiver interrupt in the applicable Interrupt Request register. 6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode functions, if desired. - Set the MULTIPROCESSOR Mode Select (MPEN) to Enable Multiprocessor mode - Set the MULTIPROCESSOR Mode Bits, MPMD[1:0], to select the desired address matching scheme - Configure the UART to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for Z8 Encore! devices without a DMA block) 7. Write the device address to the Address Compare Register (automatic multiprocessor modes only). 8. Write to the UART Control 0 register to: - Set the receive enable bit (REN) to enable the UART for data reception - Enable parity, if desired and if multiprocessor mode is not enabled, and select either even or odd parity 9. Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Check the UART Status 0 register to determine the source of the interrupt - error, break, or received data. 2. If the interrupt was caused by data available, read the data from the UART Receive Data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the MULTIPROCESSOR Mode bits MPMD[1:0]. 3. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
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4. Execute the IRET instruction to return from the interrupt-service routine and await more data.
Clear To Send (CTS) Operation
The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sampled one system clock before beginning any new character transmission. To delay transmission of the next data character, an external receiver must deassert CTS at least one system clock cycle before a new data transmission begins. For multiple character transmissions, this would typically be done during Stop Bit transmission. If CTS deasserts in the middle of a character transmission, the current character is sent completely.
MULTIPROCESSOR (9-bit) Mode
The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for selective communication when a number of processors share a common UART bus. In MULTIPROCESSOR mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is transmitted immediately following the 8-bits of data and immediately preceding the Stop bit(s) as illustrated in Figure 16. The character format is:
Data Field Idle State of Line 1 Start 0 1 2 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 MP lsb msb Stop Bit(s)
Figure 16. UART Asynchronous MULTIPROCESSOR Mode Data Format
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the MULTIPROCESSOR control bit. The UART Control 1 and Status 1 registers provide MULTIPROCESSOR (9-bit) mode control and status information. If an automatic address matching scheme is enabled, the UART Address Compare register holds the network address of the device. MULTIPROCESSOR (9-bit) Mode Receive Interrupts When MULTIPROCESSOR mode is enabled, the UART only processes frames addressed to it. The determination of whether a frame of data is addressed to the UART can be made in hardware, software or some combination of the two, depending on the multiprocessor configuration bits. In general, the address compare feature reduces the load on the CPU, since it does not need to access the UART when it receives data directed to other devices
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on the multi-node network. The following three MULTIPROCESSOR modes are available in hardware:
* * *
Interrupt on all address bytes Interrupt on matched address bytes and correctly framed data bytes Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all MULTIPROCESSOR modes, bit MPEN of the UART Control 1 Register must be set to 1. The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt service routine must manually check the address byte that caused triggered the interrupt. If it matches the UART address, the software clears MPMD[0]. At this point, each new incoming byte interrupts the CPU. The software is then responsible for determining the end of the frame. It checks for end-of-frame by reading the MPRX bit of the UART Status 1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame is different from the UART's address, then set MPMD[0] to 1 causing the UART interrupts to go inactive until the next address byte. If the new frame's address matches the UART's, the data in the new frame is processed as well. The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UART's address into the UART Address Compare Register. This mode introduces more hardware control, interrupting only on frames that match the UART's address. When an incoming address byte does not match the UART's address, it is ignored. All successive data bytes in this frame are also ignored. When a matching address byte occurs, an interrupt is issued and further interrupts now occur on each succesive data byte. The first data byte in the frame contains the NEWFRM=1 in the UART Status 1 Register. When the next address byte occurs, the hardware compares it to the UART's address. If there is a match, the interrupts continue sand the NEWFRM bit is set for the first byte of the new frame. If there is no match, then the UART ignores all incoming bytes until the next address match. The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UART's address into the UART Address Compare Register. This mode is identical to the second scheme, except that there are no interrupts on address bytes. The first data byte of each frame is still accompanied by a NEWFRM assertion.
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature reduces the software overhead associated with using a GPIO pin to control the transceiver when communicating on a multi-transceiver bus, such as RS-485. Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as illustrated in Figure 17. The Driver Enable signal asserts when a byte is written to the UART Transmit Data register. The Driver Enable signal asserts at least one UART bit period and no greater than two UART bit periods before the
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Start bit is transmitted. This timing allows a setup time to enable the transceiver. The Driver Enable signal deasserts one system clock period after the last Stop bit is transmitted. This one system clock delay allows both time for data to clear the transceiver before disabling it, as well as the ability to determine if another character follows the current character. In the event of back to back characters (new data must be written to the Transmit Data Register before the previous character is completely transmitted) the DE signal is not deasserted between characters. The DEPOL bit in the UART Control Register 1 sets the polarity of the Driver Enable signal.
1 DE 0 Data Field Idle State of Line 1 Start 0 1 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity lsb msb Stop Bit
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable to Start bit setup time is calculated as follows:
1 2 ------------------------------------ DE to Start Bit Setup Time (s) ------------------------------------ Baud Rate (Hz) Baud Rate (Hz) UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition, when the UART primary functionality is disabled, the Baud Rate Generator can also function as a basic timer with interrupt capability. Transmitter Interrupts The transmitter generates a single interrupt when the Transmit Data Register Empty bit (TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for transmission. The TDRE interrupt occurs after the Transmit shift register has shifted the first bit of data out. At this point, the Transmit Data register may be written with the next character to send. This provides 7 bit periods of latency to load the Transmit Data register before the Transmit shift register completes shifting the current character. Writing to the UART Transmit Data register clears the TDRE bit to 0.
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Receiver Interrupts The receiver generates an interrupt when any of the following occurs:
*
A data byte has been received and is available in the UART Receive Data register. This interrupt can be disabled independent of the other receiver interrupt sources. The received data interrupt occurs once the receive character has been received and placed in the Receive Data register. Software must respond to this received data available condition before the next character is completely received to avoid an overrun error. Note that in multiprocessor mode (MPEN = 1), the receive data interrupts are dependent on the multiprocessor configuration and the most recent address byte. A break is received An overrun is detected A data framing error is detected
* * *
UART Overrun Errors When an overrun error condition occurs the UART prevents overwriting of the valid data currently in the Receive Data register. The Break Detect and Overrun status bits are not displayed until after the valid data has been read. After the valid data has been read, the UART Status 0 register is updated to indicate the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that the Receive Data register contains a data byte. However, because the overrun error occurred, this byte may not contain valid data and should be ignored. The BRKD bit indicates if the overrun was caused by a break condition on the line. After reading the status byte indicating an overrun error, the Receive Data register must be read again to clear the error bits is the UART Status 0 register. Updates to the Receive Data register occur only when the next data word is received. UART Data and Error Handling Procedure Figure 18 illustrates the recommended procedure for use in UART receiver interrupt service routines.
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Receiver Ready
Receiver Interrupt
Read Status
No Errors?
Yes Read Data which clears RDA bit and resets error bits
Read Data
Discard Data
Figure 18. UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This action allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value
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(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data rate is calculated using the following equation:
System Clock Frequency (Hz) UART Data Rate (bits/s) = --------------------------------------------------------------------------------------------16 x UART Baud Rate Divisor Value
When the UART is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: 1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register to 0. 2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the BRGCTL bit in the UART Control 1 register to 1. When configured as a general purpose timer, the interrupt interval is calculated using the following equation:
Interrupt Interval (s) = System Clock Period (s) xBRG[15:0] ]
UART Control Register Definitions
The UART control registers support the UART and the associated Infrared Encoder/ Decoders. For more information on the infrared operation, refer to the Infrared Encoder/ Decoder chapter on page 120.
UART Transmit Data Register
Data bytes written to the UART Transmit Data register (Table 51) are shifted out on the TXDx pin. The Write-only UART Transmit Data register shares a Register File address with the Read-only UART Receive Data register.
Table 51. UART Transmit Data Register (UxTXD)
BITS FIELD RESET R/W ADDR
7
6
5
4
TXD X W
3
2
1
0
F40H and F48H
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TXD--Transmit Data UART transmitter data byte to be shifted out through the TXDx pin.
UART Receive Data Register
Data bytes received through the RXDx pin are stored in the UART Receive Data register (Table 52). The Read-only UART Receive Data register shares a Register File address with the Write-only UART Transmit Data register.
Table 52. UART Receive Data Register (UxRXD)
BITS FIELD RESET R/W ADDR
7
6
5
4
RXD X R
3
2
1
0
F40H and F48H
RXD--Receive Data UART receiver data byte from the RXDx pin
UART Status 0 Register
The UART Status 0 and Status 1 registers (Table 53 and 54) identify the current UART operating configuration and status.
Table 53. UART Status 0 Register (UxSTAT0)
BITS FIELD RESET R/W ADDR
7
RDA
6
PE
5
OE 0
4
FE
3
BRKD
2
TDRE
1
TXE 1
0
CTS X
R F41H and F49H
RDA--Receive Data Available This bit indicates that the UART Receive Data register has received data. Reading the UART Receive Data register clears this bit. 0 = The UART Receive Data register is empty. 1 = There is a byte in the UART Receive Data register.
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PE--Parity Error This bit indicates that a parity error has occurred. Reading the UART Receive Data register clears this bit. 0 = No parity error occurred. 1 = A parity error occurred. OE--Overrun Error This bit indicates that an overrun error has occurred. An overrun occurs when new data is received and the UART Receive Data register has not been read. If the RDA bit is reset to 0, then reading the UART Receive Data register clears this bit. 0 = No overrun error occurred. 1 = An overrun error occurred. FE--Framing Error This bit indicates that a framing error (no Stop bit following data reception) was detected. Reading the UART Receive Data register clears this bit. 0 = No framing error occurred. 1 = A framing error occurred. BRKD--Break Detect This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop bit(s) are all zeros then this bit is set to 1. Reading the UART Receive Data register clears this bit. 0 = No break occurred. 1 = A break occurred. TDRE--Transmitter Data Register Empty This bit indicates that the UART Transmit Data register is empty and ready for additional data. Writing to the UART Transmit Data register resets this bit. 0 = Do not write to the UART Transmit Data register. 1 = The UART Transmit Data register is ready to receive an additional byte to be transmitted. TXE--Transmitter Empty This bit indicates that the transmit shift register is empty and character transmission is finished. 0 = Data is currently transmitting. 1 = Transmission is complete. CTS--CTS signal When this bit is read it returns the level of the CTS signal.
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UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 54. UART Status 1 Register (UxSTAT1)
BITS FIELD RESET R/W ADDR
7
6
5
Reserved
4
3
2
1
NEWFRM
0
MPRX
0 R F44H and F4CH R/W R
Reserved--Must be 0. NEWFRM--Status bit denoting the start of a new frame. Reading the UART Receive Data register resets this bit to 0. 0 = The current byte is not the first data byte of a new frame. 1 = The current byte is the first data byte of a new frame. MPRX--Multiprocessor Receive Returns the value of the last multiprocessor bit received. Reading from the UART Receive Data register resets this bit to 0.
UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 registers (Tables 55 and 56) configure the properties of the UART's transmit and receive operations. The UART Control registers must not been written while the UART is enabled.
Table 55. UART Control 0 Register (UxCTL0)
BITS FIELD RESET R/W ADDR
7
TEN
6
REN
5
CTSE
4
PEN 0 R/W
3
PSEL
2
SBRK
1
STOP
0
LBEN
F42H and F4AH
TEN--Transmit Enable This bit enables or disables the transmitter. The enable is also controlled by the CTS signal and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
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enabled. 0 = Transmitter disabled. 1 = Transmitter enabled. REN--Receive Enable This bit enables or disables the receiver. 0 = Receiver disabled. 1 = Receiver enabled. CTSE--CTS Enable 0 = The CTS signal has no effect on the transmitter. 1 = The UART recognizes the CTS signal as an enable control from the transmitter. PEN--Parity Enable This bit enables or disables parity. Even or odd is determined by the PSEL bit. It is overridden by the MPEN bit. 0 = Parity is disabled. 1 = The transmitter sends data with an additional parity bit and the receiver receives an additional parity bit. PSEL--Parity Select 0 = Even parity is transmitted and expected on all received data. 1 = Odd parity is transmitted and expected on all received data. SBRK--Send Break This bit pauses or breaks data transmission. Sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending data before setting this bit. 0 = No break is sent. 1 = The output of the transmitter is zero. STOP--Stop Bit Select 0 = The transmitter sends one stop bit. 1 = The transmitter sends two stop bits. LBEN--Loop Back Enable 0 = Normal operation. 1 = All transmitted data is looped back to the receiver.
Table 56. UART Control 1 Register (UxCTL1)
BITS FIELD RESET R/W ADDR
7
MPMD[1]
6
MPEN
5
MPMD[0]
4
MPBT 0 R/W
3
DEPOL
2
BRGCTL
1
RDAIRQ
0
IREN
F43H and F4BH
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MPMD[1:0]--MULTIPROCESSOR Mode If MULTIPROCESSOR (9-bit) mode is enabled, 00 = The UART generates an interrupt request on all received bytes (data and address). 01 = The UART generates an interrupt request only on received address bytes. 10 = The UART generates an interrupt request when a received address byte matches the value stored in the Address Compare Register and on all successive data bytes until an address mismatch occurs. 11 = The UART generates an interrupt request on all received data bytes for which the most recent address byte matched the value in the Address Compare Register. MPEN--MULTIPROCESSOR (9-bit) Enable This bit is used to enable MULTIPROCESSOR (9-bit) mode. 0 = Disable MULTIPROCESSOR (9-bit) mode. 1 = Enable MULTIPROCESSOR (9-bit) mode. MPBT--MULTIPROCESSOR Bit Transmit This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled. 0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit). 1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit). DEPOL--Driver Enable Polarity 0 = DE signal is Active High. 1 = DE signal is Active Low. BRGCTL--Baud Rate Control This bit causes different UART behavior depending on whether the UART receiver is enabled (REN = 1 in the UART Control 0 Register). When the UART receiver is not enabled, this bit determines whether the Baud Rate Generator issues interrupts. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value 1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0. Reads from the Baud Rate High and Low Byte registers return the current BRG count value. When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to return the BRG count value instead of the Reload Value. 0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value. 1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count value. Unlike the Timers, there is no mechanism to latch the High Byte when the Low Byte is read. RDAIRQ--Receive Data Interrupt Enable 0 = Received data and receiver errors generates an interrupt request to the Interrupt Controller. 1 = Received data does not generate an interrupt request to the Interrupt Controller. Only receiver errors generate an interrupt request.
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IREN--Infrared Encoder/Decoder Enable 0 = Infrared Encoder/Decoder is disabled. UART operates normally operation. 1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through the Infrared Encoder/Decoder.
UART Address Compare Register
The UART Address Compare register (Table 57) stores the multi-node network address of the UART. When the MPMD[1] bit of UART Control Register 0 is set, all incoming address bytes are compared to the value stored in the Address Compare register. Receive interrupts and RDA assertions only occur in the event of a match.
Table 57. UART Address Compare Register (UxADDR)
BITS FIELD RESET R/W ADDR
7
6
5
4
3
2
1
0
COMP_ADDR 0 R/W F45H and F4DH
COMP_ADDR--Compare Address This 8-bit value is compared to the incoming address bytes.
UART Baud Rate High and Low Byte Registers
The UART Baud Rate High and Low Byte registers (Tables 58 and 59) combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: 1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 register to 0. 2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the BRGCTL bit in the UART Control 1 register to 1. When congured as a general purpose timer, the UART BRG interrupt interval is calculated using the following equation:
UART BRG Interrupt Interval (s) = System Clock Period (s) xBRG[15:0] ]
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Table 58. UART Baud Rate High Byte Register (UxBRH)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRH 1 R/W
3
2
1
0
F46H and F4EH
Table 59. UART Baud Rate Low Byte Register (UxBRL)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRL 1 R/W
3
2
1
0
F47H and F4FH
For a given UART data rate, the integer baud rate divisor value is calculated using the following equation:
System Clock Frequency (Hz) UART Baud Rate Divisor Value (BRG) = Round --------------------------------------------------------------------------- 16 x UART Data Rate (bits/s)
The baud rate error relative to the desired baud rate is calculated using the following equation:
Actual Data Rate Desired Data Rate UART Baud Rate Error (%) = 100 x -------------------------------------------------------------------------------------------------- Desired Data Rate
For reliable communication, the UART baud rate error must never exceed 5 percent. Table 60 provides information on data rate errors for popular baud rates and commonly used crystal oscillator frequencies.
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Table 60. UART Baud Rates
20.0 MHz System Clock Desired Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 BRG Divisor (Decimal) 1 2 5 11 22 33 65 130 260 521 1042 2083 4167 Actual Rate (kHz) 1250.0 625.0 250.0 113.6 56.8 37.9 19.2 9.62 4.81 2.40 1.20 0.60 0.30 Error (%) 0.00 0.00 0.00 -1.36 -1.36 -1.36 0.16 0.16 0.16 -0.03 -0.03 0.02 -0.01 18.432 MHz System Clock Desired Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 BRG Divisor (Decimal) 1 2 5 10 20 30 60 120 240 480 960 1920 3840 Actual Rate (kHz) 1152.0 576.0 230.4 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 Error (%) -7.84% -7.84% -7.84% 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
16.667 MHz System Clock Desired Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 BRG Divisor (Decimal) 1 2 4 9 18 27 54 109 217 434 868 1736 Actual Rate (kHz) 1041.69 520.8 260.4 115.7 57.87 38.6 19.3 9.56 4.80 2.40 1.20 0.60 Error (%) -16.67 -16.67 4.17 0.47 0.47 0.47 0.47 -0.45 -0.83 0.01 0.01 0.01
11.0592 MHz System Clock Desired Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 BRG Divisor (Decimal) N/A 1 3 6 12 18 36 72 144 288 576 1152 Actual Rate (kHz) N/A 691.2 230.4 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 Error (%) N/A 10.59 -7.84 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
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Table 60. UART Baud Rates (Continued)
0.30 3472 0.30 0.01 0.30 2304 0.30 0.00
10.0 MHz System Clock Desired Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 BRG Divisor (Decimal) N/A 1 3 5 11 16 33 65 130 260 521 1042 2083 Actual Rate (kHz) N/A 625.0 208.33 125.0 56.8 39.1 18.9 9.62 4.81 2.40 1.20 0.60 0.30 Error (%) N/A 0.00 -16.67 8.51 -1.36 1.73 0.16 0.16 0.16 -0.03 -0.03 -0.03 0.2
5.5296 MHz System Clock Desired Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 BRG Divisor (Decimal) N/A N/A 1 3 6 9 18 36 72 144 288 576 1152 Actual Rate (kHz) N/A N/A 345.6 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 0.60 0.30 Error (%) N/A N/A 38.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
3.579545 MHz System Clock Desired Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 BRG Divisor (Decimal) N/A N/A 1 2 4 6 12 23 47 93 186 Actual Rate (kHz) N/A N/A 223.72 111.9 55.9 37.3 18.6 9.73 4.76 2.41 1.20 Error (%) N/A N/A -10.51 -2.90 -2.90 -2.90 -2.90 1.32 -0.83 0.23 0.23
1.8432 MHz System Clock Desired Rate (kHz) 1250.0 625.0 250.0 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 BRG Divisor (Decimal) N/A N/A N/A 1 2 3 6 12 24 48 96 Actual Rate (kHz) N/A N/A N/A 115.2 57.6 38.4 19.2 9.60 4.80 2.40 1.20 Error (%) N/A N/A N/A 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
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Table 60. UART Baud Rates (Continued)
0.60 0.30 373 746 0.60 0.30 -0.04 -0.04 0.60 0.30 192 384 0.60 0.30 0.00 0.00
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Infrared Encoder/Decoder
Overview
The 64K Series products contain two fully-functional, high-performance UART to Infrared Encoder/Decoders (Endecs). Each Infrared Endec is integrated with an on-chip UART to allow easy communication between the 64K Series and IrDA Physical Layer Specification, Version 1.3-compliant infrared transceivers. Infrared communication provides secure, reliable, low-cost, point-to-point communication between PCs, PDAs, cell phones, printers and other infrared enabled devices.
Architecture
Figure 19 illustrates the architecture of the Infrared Endec.
System Clock RxD TxD UART Baud Rate Clock Infrared Encoder/Decoder (Endec) RXD
ZiLOG ZHX1810 RXD TXD TXD Infrared Transceiver
Interrupt I/O Signal Address
Data
Figure 19. Infrared Data Communication System Block Diagram
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Operation
When the Infrared Endec is enabled, the transmit data from the associated on-chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infrared transceiver via the TXD pin. Likewise, data received from the infrared transceiver is passed to the Infrared Endec via the RXD pin, decoded by the Infrared Endec, and then passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the UART's Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared Endec data rate is calculated using the following equation:
System Clock Frequency (Hz) Infrared Data Rate (bits/s) = --------------------------------------------------------------------------------------------16 x UART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The UART's transmit signal (TXD) and baud rate clock are used by the IrDA to generate the modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared data bit is 16-clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains low for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is output following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is output to complete the full 16-clock data period. Figure 20 illustrates IrDA data transmission. When the Infrared Endec is enabled, the UART's TXD signal is internal to the 64K Series products while the IR_TXD signal is output through the TXD pin.
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16-clock period
Baud Rate Clock
UART's TXD
Start Bit = 0 3-clock pulse
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_TXD 7-clock delay
Figure 20. Infrared Data Transmission
Receiving IrDA Data
Data received from the infrared transceiver via the IR_RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART. The UART's baud rate clock is used by the Infrared Endec to generate the demodulated signal (RXD) that drives the UART. Each UART/Infrared data bit is 16-clocks wide. Figure 21 illustrates data reception. When the Infrared Endec is enabled, the UART's RXD signal is internal to the 64K Series products while the IR_RXD signal is received through the RXD pin.
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16-clock period
Baud Rate Clock Start Bit = 0 IR_RXD min. 1.6s pulse UART's RXD 8-clock delay Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
16-clock period
16-clock period
16-clock period
16-clock period
Figure 21. Infrared Data Reception
Caution:
The system clock frequency must be at least 1.0MHz to ensure proper reception of the 1.6s minimum width pulses allowed by the IrDA standard.
Endec Receiver Synchronization The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate an input stream for the UART and to create a sampling window for detection of incoming pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods with respect to the incoming IrDA data stream. When a falling edge in the input data stream is detected, the Endec counter is reset. When the count reaches a value of 8, the UART RXD value is updated to reflect the value of the decoded data. When the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. The window remains open until the count again reaches 8 (or in other words 24 baud clock periods since the previous pulse was detected). This gives the Endec a sampling window of minus four baudrate clocks to plus eight baudrate clocks around the expected time of an incoming pulse. If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state and waits for the next falling edge. As each falling edge is detected, the Endec clock counter is reset, resynchronizing the Endec to the incoming signal. This action allows the Endec to tolerate jitter and baud rate errors in the incoming data stream. Resynchronizing the Endec does not alter the operation of the UART, which ultimately receives the data. The UART is only synchronized to the incoming data stream when a Start bit is received.
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Infrared Encoder/Decoder Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control registers as defined beginning on page 109. Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the UARTx Control 1 register to 1 to enable the Infrared Encoder/ Decoder before enabling the GPIO Port alternate function for the corresponding pin.
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Serial Peripheral Interface
Overview
The Serial Peripheral InterfaceTM (SPI) is a synchronous interface allowing several SPItype devices to be interconnected. SPI-compatible devices include EEPROMs, Analog-toDigital Converters, and ISDN devices. Features of the SPI include:
* * * * * Architecture
Full-duplex, synchronous, character-oriented communication Four-wire interface Data transfers rates up to a maximum of one-half the system clock frequency Error detection Dedicated Baud Rate Generator
The SPI may be configured as either a Master (in single or multi-master systems) or a Slave as illustrated in Figures 22 through 24.
SPI Master
To Slave's SS Pin From Slave
SS MISO 8-bit Shift Register Bit 0 MOSI Bit 7
To Slave
To Slave
SCK
Baud Rate Generator
Figure 22. SPI Configured as a Master in a Single Master, Single Slave System
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VCC
SPI Master SS To Slave #2's SS Pin To Slave #1's SS Pin From Slave MISO To Slave MOSI GPIO GPIO 8-bit Shift Register Bit 0 Bit 7
To Slave
SCK
Baud Rate Generator
Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System
SPI Slave From Master SS
To Master
MISO
8-bit Shift Register Bit 7 Bit 0
From Master
MOSI
From Master
SCK
Figure 24. SPI Configured as a Slave
Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (serial clock, transmit, receive and Slave select). The SPI block consists of a transmit/receive shift register, a Baud Rate (clock) Generator and a control unit.
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During an SPI transfer, data is sent and received simultaneously by both the Master and the Slave SPI devices. Separate signals are required for data and the serial clock. When an SPI transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift register in the Master and another 8-bit shift register in the Slave are connected as a circular buffer. The SPI shift register is single-buffered in the transmit and receive directions. New data to be transmitted cannot be written into the shift register until the previous transmission is complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
* * * *
MISO (Master-In, Slave-Out) MOSI (Master-Out, Slave-In) SCK (SPI Serial Clock) SS (Slave Select)
The following paragraphs discuss these SPI signals. Each signal is described in both Master and Slave modes. Master-In, Slave-Out The Master-In, Slave-Out (MISO) pin is configured as an input in a Master device and as an output in a Slave device. It is one of the two lines that transfer serial data, with the most significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance state if the Slave is not selected. When the SPI is not enabled, this signal is in a highimpedance state. Master-Out, Slave-In The Master-Out, Slave-In (MOSI) pin is configured as an output in a Master device and as an input in a Slave device. It is one of the two lines that transfer serial data, with the most significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance state. Serial Clock The Serial Clock (SCK) synchronizes data movement both in and out of the device through its MOSI and MISO pins. In MASTER mode, the SPI's Baud Rate Generator creates the serial clock. The Master drives the serial clock out its own SCK pin to the Slave's SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock signal from the Master synchronizes the data transfer between the Master and Slave devices. Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times the system (XIN) clock period.
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The Master and Slave are each capable of exchanging a character of data during a sequence of NUMBITS clock cycles (refer to NUMBITS field in the SPIMODE register). In both Master and Slave SPI devices, data is shifted on one edge of the SCK and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI phase and polarity control. Slave Select The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low prior to all data communication to and from the Slave device. SS must stay Low for the full duration of each character transferred. The SS signal may stay Low during the transfer of multiple characters or may deassert between each character. When the SPI is configured as the only Master in an SPI system, the SS pin can be set as either an input or an output. For communication between the Z8F642x familyZ8R642x family device's SPI Master and external Slave devices, the SS signal, as an output, can assert the SS input pin on one of the Slave devices. Other GPIO output pins can also be employed to select external SPI Slave devices. When the SPI is configured as one Master in a multi-master SPI system, the SS pin must be set as an input. The SS input signal on the Master must be High. If the SS signal goes Low (indicating another Master is driving the SPI bus), a Collision error flag is set in the SPI Status register.
SPI Clock Phase and Polarity Control
The SPI supports four combinations of serial clock phase and polarity using two bits in the SPI Control register. The clock polarity bit, CLKPOL, selects an active high or active low clock and has no effect on the transfer format. Table 61 lists the SPI Clock Phase and Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamentally different transfer formats. For proper data transmission, the clock phase and polarity must be identical for the SPI Master and the SPI Slave. The Master always places data on the MOSI line a half-cycle before the receive clock edge (SCK signal), in order for the Slave to latch the data.
Table 61. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation SCK Transmit Edge Falling Rising Rising Falling SCK Receive Edge Rising Falling Falling Rising SCK Idle State Low High Low High
PHASE
0 0 1 1
CLKPOL
0 1 0 1
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Transfer Format PHASE Equals Zero Figure 25 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to 0. The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to one. The diagram may be interpreted as either a Master or Slave timing diagram because the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly connected between the Master and the Slave.
SCK (CLKPOL = 0)
SCK (CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 25. SPI Timing When PHASE is 0
Transfer Format PHASE Equals One Figure 26 illustrates the timing diagram for an SPI transfer in which PHASE is one. Two waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for CLKPOL set to 1.
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SCK (CLKPOL = 0)
SCK (CLKPOL = 1)
MOSI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MISO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Input Sample Time
SS
Figure 26. SPI Timing When PHASE is 1
Multi-Master Operation
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied together and all MISO pins are tied together. All SPI pins must then be configured in open-drain mode to prevent bus contention. At any one time, only one SPI device is configured as the Master and all other SPI devices on the bus are configured as Slaves. The Master enables a single Slave by asserting the SS pin on that Slave only. Then, the single Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves (including those which are not enabled). The enabled Slave drives data out its MISO pin to the MISO Master pin. For a Master device operating in a multi-master system, if the SS pin is configured as an input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status Register. The COL bit indicates the occurrence of a multi-master collision (mode fault error condition).
Slave Operation
The SPI block is configured for slave mode operation by setting the SPIEN bit to 1 and the MMEN bit to 0 in the SPICTL register and setting the SSIO bit to 0 in the SPIMODE reg-
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ister. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL register and the NUMBITS field in the SPIMODE register must be set to be consistent with the other SPI devices. The STR bit in the SPICTL register may be used if desired to force a "startup" interrupt. The BIRQ bit in the SPICTL register and the SSV bit in the SPIMODE register are not used in slave mode. The SPI baud rate generator is not used in slave mode so the SPIBRH and SPIBRL registers need not be initialized. If the slave has data to send to the master, the data must be written to the SPIDAT register before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT register is not written prior to the slave transaction, the MISO pin outputs whatever value is currently in the SPIDAT register. Due to the delay resulting from synchronization of the SPI input signals to the internal system clock, the maximum SPICLK baud rate that can be supported in slave mode is the system clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic to support SPI communication protocols and recognize when communication errors have occurred. The SPI Status register indicates when a data transmission error has been detected. Overrun (Write Collision) An overrun error (write collision) indicates a write to the SPI Data register was attempted while a data transfer is in progress (in either master or slave modes). An overrun sets the OVR bit in the SPI Status register to 1. Writing a 1 to OVR clears this error flag. The data register is not altered when a write occurs while data transfer is in progress. Mode Fault (Multi-Master Collision) A mode fault indicates when more than one Master is trying to communicate at the same time (a multi-master collision). The mode fault is detected when the enabled Master's SS pin is asserted. A mode fault sets the COL bit in the SPI Status register to 1. Writing a 1 to COL clears this error flag. Slave Mode Abort In slave mode of operation if the SS pin deasserts before all bits in a character have been transferred, the transaction is aborted. When this condition occurs the ABT bit is set in the SPISTAT register as well as the IRQ bit (indicating the transaction is complete). The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous transaction left off. Writing a 1 to ABT clears this error flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmission/reception completes in both master and slave modes. A character can be defined to be
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1 through 8 bits by the NUMBITS field in the SPI Mode register. In slave mode it is not necessary for SS to deassert between characters to generate the interrupt. The SPI in Slave mode can also generate an interrupt if the SS signal deasserts prior to transfer of all the bits in a character (see description of slave abort error above). Writing a 1 to the IRQ bit in the SPI Status Register clears the pending SPI interrupt request. The IRQ bit must be cleared to 0 by the Interrupt Service Routine to generate future interrupts. To start the transfer process, an SPI interrupt may be forced by software writing a 1 to the STR bit in the SPICTL register. If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator timeout. This timer function must be enabled by setting the BIRQ bit in the SPICTL register. This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT register, just the SPI interrupt bit in the interrupt controller.
SPI Baud Rate Generator
In SPI Master mode, the Baud Rate Generator creates a lower frequency serial clock (SCK) for data transmission synchronization between the Master and the external Slave. The input to the Baud Rate Generator is the system clock. The SPI Baud Rate High and Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator. The SPI baud rate is calculated using the following equation:
System Clock Frequency (Hz) SPI Baud Rate (bits/s) = --------------------------------------------------------------------------2 x BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value of (2 X 65536 = 131072). When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: 1. Disable the SPI by clearing the SPIEN bit in the SPI Control register to 0. 2. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the SPI Control register to 1. When configured as a general purpose timer, the interrupt interval is calculated using the following equation:
Interrupt Interval (s) = System Clock Period (s) xBRG[15:0] ]
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SPI Control Register Definitions
SPI Data Register
The SPI Data register (Table 62) stores both the outgoing (transmit) data and the incoming (receive) data. Reads from the SPI Data register always return the current contents of the 8-bit shift register. Data is shifted out starting with bit 7. The last bit received resides in bit position 0. With the SPI configured as a Master, writing a data byte to this register initiates the data transmission. With the SPI configured as a Slave, writing a data byte to this register loads the shift register in preparation for the next data transfer with the external Master. In either the Master or Slave modes, if a transmission is already in progress, writes to this register are ignored and the Overrun error flag, OVR, is set in the SPI Status register. When the character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode register), the transmit character must be left justified in the SPI Data register. A received character of less than 8 bits is right justified (last bit received is in bit position 0). For example, if the SPI is configured for 4-bit characters, the transmit characters must be written to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
Table 62. SPI Data Register (SPIDATA)
BITS FIELD RESET R/W ADDR
7
6
5
4
DATA X R/W F60H
3
2
1
0
DATA--Data Transmit and/or receive data.
SPI Control Register
The SPI Control register (Table 63) configures the SPI for transmit and receive operations.
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Table 63. SPI Control Register (SPICTL)
BITS FIELD RESET R/W ADDR
7
IRQE
6
STR
5
BIRQ
4
PHASE 0 R/W F61H
3
CLKPOL
2
WOR
1
MMEN
0
SPIEN
IRQE--Interrupt Request Enable 0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller. 1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller. STR--Start an SPI Interrupt Request 0 = No effect. 1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1. Setting this bit forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by software for a function similar to transmit buffer empty in a UART. Writing a 1 to the IRQ bit in the SPI Status register clears this bit to 0. BIRQ--BRG Timer Interrupt Request If the SPI is enabled, this bit has no effect. If the SPI is disabled: 0 = The Baud Rate Generator timer function is disabled. 1 = The Baud Rate Generator timer function and time-out interrupt are enabled. PHASE--Phase Select Sets the phase relationship of the data to the clock. Refer to the SPI Clock Phase and Polarity Control section for more information on operation of the PHASE bit. CLKPOL--Clock Polarity 0 = SCK idles Low (0). 1 = SCK idle High (1). WOR--Wire-OR (Open-Drain) Mode Enabled 0 = SPI signal pins not configured for open-drain. 1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function. This setting is typically used for multi-master and/or multi-slave configurations. MMEN--SPI Master Mode Enable 0 = SPI configured in Slave mode. 1 = SPI configured in Master mode. SPIEN--SPI Enable 0 = SPI disabled. 1 = SPI enabled.
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SPI Status Register
The SPI Status register (Table 64) indicates the current state of the SPI. All bits revert to their reset state if the SPIEN bit in the SPICTL register = 0.
Table 64. SPI Status Register (SPISTAT)
BITS FIELD RESET R/W ADDR
7
IRQ
6
OVR
5
COL
4
ABT 0
3
Reserved
2
1
TXST
0
SLAS 1
R/W* F62H
R
R/W* = Read access. Write a 1 to clear the bit to 0.
IRQ--Interrupt Request If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud Rate Generator is used as a timer to generate the SPI interrupt. 0 = No SPI interrupt request pending. 1 = SPI interrupt request is pending. OVR--Overrun 0 = An overrun error has not occurred. 1 = An overrun error has been detected. COL--Collision 0 = A multi-master collision (mode fault) has not occurred. 1 = A multi-master collision (mode fault) has been detected. ABT--Slave mode transaction abort This bit is set if the SPI is configured in slave mode, a transaction is occurring and SS deasserts before all bits of a character have been transferred as defined by the NUMBITS field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has completed. 0 = A slave mode transaction abort has not occurred. 1 = A slave mode transaction abort has been detected. Reserved--Must be 0. TXST--Transmit Status 0 = No data transmission currently in progress. 1 = Data transmission currently in progress.
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SLAS--Slave Select If SPI enabled as a Slave, 0 = SS input pin is asserted (Low) 1 = SS input is not asserted (High). If SPI enabled as a Master, this bit is not applicable.
SPI Mode Register
The SPI Mode register (Table 65) configures the character bit width and the direction and value of the SS pin.
Table 65. SPI Mode Register (SPIMODE)
BITS FIELD RESET R/W ADDR
7
Reserved
6
5
DIAG
4
3
NUMBITS[2:0] 0
2
1
SSIO
0
SSV
R F63H
R/W
Reserved--Must be 0. DIAG - Diagnostic Mode Control bit This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be read using the SPIBRH and SPIBRL register locations. 0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers 1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading SPIBRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High and Low byte values are not buffered. Caution: Exercise caution if reading the values while the BRG is counting.
NUMBITS[2:0]--Number of Data Bits Per Character to Transfer This field contains the number of bits to shift for each character transfer. Refer to the SPI Data Register description for information on valid bit positions when the character length is less than 8-bits. 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bits
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110 = 6 bits 111 = 7 bits. SSIO--Slave Select I/O 0 = SS pin configured as an input. 1 = SS pin configured as an output (Master mode only). SSV--Slave Select Value If SSIO = 1 and SPI configured as a Master: 0 = SS pin driven Low (0). 1 = SS pin driven High (1). This bit has no effect if SSIO = 0 or SPI configured as a Slave.
SPI Diagnostic State Register
The SPI Diagnostic State register (Table 66) provides observability of internal state. This is a read only register used for SPI diagnostics.
Table 66. SPI Diagnostic State Register (SPIDST)
BITS FIELD RESET R/W ADDR
7
SCKEN
6
TCKEN
5
4
3
2
SPISTATE
1
0
0 R F64H
SCKEN - Shift Clock Enable 0 = The internal Shift Clock Enable signal is deasserted 1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next system clock) TCKEN - Transmit Clock Enable 0 = The internal Transmit Clock Enable signal is deasserted. 1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial data out is updated on the next system clock (MOSI or MISO). SPISTATE - SPI State Machine Defines the current state of the internal SPI State Machine.
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SPI Baud Rate High and Low Byte Registers
The SPI Baud Rate High and Low Byte registers (Tables 67 and 68) combine to form a 16bit reload value, BRG[15:0], for the SPI Baud Rate Generator. When congured as a general purpose timer, the SPI BRG interrupt interval is calculated using the following equation:
SPI BRG Interrupt Interval (s) = System Clock Period (s) xBRG[15:0] ].
Table 67. SPI Baud Rate High Byte Register (SPIBRH)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRH 1 R/W F66H
3
2
1
0
BRH = SPI Baud Rate High Byte Most significant byte, BRG[15:8], of the SPI Baud Rate Generator's reload value.
Table 68. SPI Baud Rate Low Byte Register (SPIBRL)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRL 1 R/W F67H
3
2
1
0
BRL = SPI Baud Rate Low Byte Least significant byte, BRG[7:0], of the SPI Baud Rate Generator's reload value.
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I2C Controller
Overview
The I2C Controller makes the 64K Series products bus-compatible with the I2CTM protocol. The I2C Controller consists of two bidirectional bus lines--a serial data signal (SDA) and a serial clock signal (SCL). Features of the I2C Controller include:
* * * *
Transmit and Receive Operation in MASTER mode Maximum data rate of 400kbit/sec 7- and 10-bit addressing modes for Slaves Unrestricted number of data bytes transmitted per transfer
The I2C Controller in the 64K Series products does not operate in Slave mode.
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Architecture
Figure 27 illustrates the architecture of the I2C Controller.
SDA SCL
Shift ISHIFT Load Baud Rate Generator I2CBRH I2CBRL I2CDATA
Receive
Tx/Rx State Machine
I2CCTL
I2CSTAT
I2C Interrupt
Register Bus
Figure 27. I2C Controller Block Diagram
Operation
The I2C Controller operates in MASTER mode to transmit and receive data. Only a single master is supported. Arbitration between two masters must be accomplished in software. I2C supports the following operations:
* *
Master transmits to a 7-bit slave Master transmits to a 10-bit slave
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* *
Master receives from a 7-bit slave Master receives from a 10-bit slave
SDA and SCL Signals
I2C sends all addresses, data and acknowledge signals over the SDA line, most-significant bit first. SCL is the common clock for the I2C Controller. When the SDA and SCL pin alternate functions are selected for their respective GPIO ports, the pins are automatically configured for open-drain operation. The master (I2C) is responsible for driving the SCL clock signal, although the clock signal can become skewed by a slow slave device. During the low period of the clock, the slave pulls the SCL signal Low to suspend the transaction. The master releases the clock at the end of the low period and notices that the clock remains low instead of returning to a high level. When the slave releases the clock, the I2C Controller continues the transaction. All data is transferred in bytes and there is no limit to the amount of data transferred in one operation. When transmitting data or acknowledging read data from the slave, the SDA signal changes in the middle of the low period of SCL and is sampled in the middle of the high period of SCL.
I2C Interrupts
The I2C Controller contains four sources of interrupts--Transmit, Receive, Not Acknowledge and baud rate generator. These four interrupt sources are combined into a single interrupt request signal to the Interrupt Controller. The Transmit interrupt is enabled by the IEN and TXI bits of the Control register. The Receive and Not Acknowledge interrupts are enabled by the IEN bit of the Control register. The baud rate generator interrupt is enabled by the BIRQ and IEN bits of the Control register. Not Acknowledge interrupts occur when a Not Acknowledge condition is received from the slave or sent by the I2C Controller and neither the START or STOP bit is set. The Not Acknowledge event sets the NCKI bit of the I2C Status register and can only be cleared by setting the START or STOP bit in the I2C Control register. When this interrupt occurs, the I2C Controller waits until either the STOP or START bit is set before performing any action. In an interrupt service routine, the NCKI bit should always be checked prior to servicing transmit or receive interrupt conditions because it indicates the transaction is being terminated. Receive interrupts occur when a byte of data has been received by the I2C Controller (master reading data from slave). This procedure sets the RDRF bit of the I2C Status register. The RDRF bit is cleared by reading the I2C Data register. The RDRF bit is set during the acknowledge phase. The I2C Controller pauses after the acknowledge phase until the receive interrupt is cleared before performing any other action.
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Transmit interrupts occur when the TDRE bit of the I2C Status register sets and the TXI bit in the I2C Control register is set. Transmit interrupts occur under the following conditions when the transmit data register is empty:
* * * *
The I2C Controller is enabled The first bit of the byte of an address is shifting out and the RD bit of the I2C Status register is deasserted. The first bit of a 10-bit address shifts out. The first bit of write data shifts out.
Note: Writing to the I2C Data register always clears the TRDE bit to 0. When TDRE is asserted, the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently shifting out until the Data register is written with the next value to send or the STOP or START bits are set indicating the current byte is the last one to send. The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled (IEN bit in the I2CCTL register = 0) and the BIRQ bit in the I2CCTL register = 1, an interrupt is generated when the baud rate generator counts down to 1. This allows the I2C baud rate generator to be used by software as a general purpose timer when IEN = 0.
Software Control of I2C Transactions
Software can control I2C transactions by using the I2C Controller interrupt, by polling the I2C Status register or by DMA. Note that not all products include a DMA Controller. To use interrupts, the I2C interrupt must be enabled in the Interrupt Controller. The TXI bit in the I2C Control register must be set to enable transmit interrupts. To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the I2C Status register should be polled. The TDRE bit asserts regardless of the state of the TXI bit. Either or both transmit and receive data movement can be controlled by the DMA Controller. The DMA Controller channel(s) must be initialized to select the I2C transmit and receive requests. Transmit DMA requests require that the TXI bit in the I2C Control register be set. Caution: A transmit (write) DMA operation hangs if the slave responds with a Not Acknowledge before the last byte has been sent. After receiving the Not Acknowledge, the I2C Controller sets the NCKI bit in the Status register and pauses until either the STOP or START bits in the Control register are set.
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In order for a receive (read) DMA transaction to send a Not Acknowledge on the last byte, the receive DMA must be set up to receive n-1 bytes, then software must set the NAK bit and receive the last (nth) byte directly.
Start and Stop Conditions
The master (I2C) drives all Start and Stop signals and initiates all transactions. To start a transaction, the I2C Controller generates a START condition by pulling the SDA signal Low while SCL is High. To complete a transaction, the I2C Controller generates a Stop condition by creating a low-to-high transition of the SDA signal while the SCL signal is high. The START and STOP bits in the I2C Control register control the sending of the Start and Stop conditions. A master is also allowed to end one transaction and begin a new one by issuing a Restart. This is accomplished by setting the START bit at the end of a transaction, rather than the STOP bit. Note that the Start condition not sent until the START bit is set and data has been written to the I2C Data register.
Master Write and Read Transactions
The following sections provide a recommended procedure for performing I2C write and read transactions from the I2C Controller (master) to slave I2C devices. In general software should rely on the TDRE, RDRF and NCKI bits of the status register (these bits generate interrupts) to initiate software actions. When using interrupts or DMA, the TXI bit is set to start each transaction and cleared at the end of each transaction to eliminate a "trailing" Transmit interrupt. Caution should be used in using the ACK status bit within a transaction because it is difficult for software to tell when it is updated by hardware. When writing data to a slave, the I2C pauses at the beginning of the Acknowledge cycle if the data register has not been written with the next value to be sent (TDRE bit in the I2C Status register = 1). In this scenario where software is not keeping up with the I2C bus (TDRE asserted longer than one byte time), the Acknowledge clock cycle for byte n is delayed until the Data register is written with byte n + 1, and appears to be grouped with the data clock cycles for byte n+1. If either the START or STOP bit is set, the I2C does not pause prior to the Acknowledge cycle because no additional data is sent. When a Not Acknowledge condition is received during a write (either during the address or data phases), the I2C Controller generates the Not Acknowledge interrupt (NCKI = 1) and pause until either the STOP or START bit is set. Unless the Not Acknowledge was received on the last byte, the Data register will already have been written with the next address or data byte to send. In this case the FLUSH bit of the Control register should be set at the same time the STOP or START bit is set to remove the stale transmit data and enable subsequent Transmit interrupts. When reading data from the slave, the I2C pauses after the data Acknowledge cycle until the receive interrupt is serviced and the RDRF bit of the status register is cleared by read-
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ing the I2C Data register. Once the I2C data register has been read, the I2C reads the next data byte.
Address Only Transaction with a 7-bit Address
In the situation where software determines if a slave with a 7-bit address is responding without sending or receiving data, a transaction can be done which only consists of an address phase. Figure 28 illustrates this "address only" transaction to determine if a slave with a 7-bit address will acknowledge. As an example, this transaction can be used after a "write" has been done to a EEPROM to determine when the EEPROM completes its internal write operation and is once again responding to I2C transactions. If the slave does not Acknowledge, the transaction can be repeated until the slave does Acknowledge.
S Slave Address W = 0 A/A P
Figure 28. 7-Bit Address Only Transaction Format
The procedure for an address only transaction to a 7-bit addressed slave is as follows: 1. Software asserts the IEN bit in the I2C Control register. 2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. 3. The I2C interrupt asserts, because the I2C Data register is empty (TDRE = 1) 4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0) to the I2C Data register. As an alternative this could be a read operation instead of a write operation. 5. Software sets the START and STOP bits of the I2C Control register and clears the TXI bit. 6. The I2C Controller sends the START condition to the I2C slave. 7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 8. Software polls the STOP bit of the I2C Control register. Hardware deasserts the STOP bit when the address only transaction is completed. 9. Software checks the ACK bit of the I2C Status register. If the slave acknowledged, the ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI interrupt does not occur in the not acknowledge case because the STOP bit was set.
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Write Transaction with a 7-Bit Address
Figure 29 illustrates the data transfer format for a 7-bit addressed slave. Shaded regions indicate data transferred from the I2C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I2C Controller.
S Slave Address W=0 A Data A Data A Data A/A P/S
Figure 29. 7-Bit Addressed Slave Data Transfer Format
The procedure for a transmit operation to a 7-bit addressed slave is as follows: 1. Software asserts the IEN bit in the I2C Control register. 2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. 3. The I2C interrupt asserts, because the I2C Data register is empty 4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0) to the I2C Data register. 5. Software asserts the START bit of the I2C Control register. 6. The I2C Controller sends the START condition to the I2C slave. 7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 8. After one bit of address has been shifted out by the SDA signal, the Transmit interrupt is asserted (TDRE = 1). 9. Software responds by writing the transmit data into the I2C Data register. 10. The I2C Controller shifts the rest of the address and write bit out by the SDA signal. 11. If the I2C slave sends an acknowledge (by pulling the SDA signal low) during the next high period of SCL the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 12. If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is set in the Status register, ACK bit is cleared). Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore following steps). 12. The I2C Controller loads the contents of the I2C Shift register with the contents of the I2C Data register.
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13. The I2C Controller shifts the data out of using the SDA signal. After the first bit is sent, the Transmit interrupt is asserted. 14. If more bytes remain to be sent, return to step 9. 15. Software responds by setting the STOP bit of the I2C Control register (or START bit to initiate a new transaction). In the STOP case, software clears the TXI bit of the I2C Control register at the same time. 16. The I2C Controller completes transmission of the data on the SDA signal. 17. The slave may either Acknowledge or Not Acknowledge the last byte. Because either the STOP or START bit is already set, the NCKI interrupt does not occur. 18. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus. The STOP or START bit is cleared.
Address Only Transaction with a 10-bit Address
In the situation where software wants to determine if a slave with a 10-bit address is responding without sending or receiving data, a transaction can be done which only consists of an address phase. Figure 30 illustrates this "address only" transaction to determine if a slave with 10-bit address will acknowledge. As an example, this transaction can be used after a "write" has been done to a EEPROM to determine when the EEPROM completes its internal write operation and is once again responding to I2C transactions. If the slave does not Acknowledge the transaction can be repeated until the slave is able to Acknowledge.
Slave Address 1st 7 bits Slave Address 2nd Byte
S
W = 0 A/A
A/A P
Figure 30. 10-Bit Address Only Transaction Format
The procedure for an address only transaction to a 10-bit addressed slave is as follows: 1. Software asserts the IEN bit in the I2C Control register. 2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. 3. The I2C interrupt asserts, because the I2C Data register is empty (TDRE = 1) 4. Software responds to the TDRE interrupt by writing the first slave address byte. The least-significant bit must be 0 for the write operation. 5. Software asserts the START bit of the I2C Control register. 6. The I2C Controller sends the START condition to the I2C slave.
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7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is asserted. 9. Software responds by writing the second byte of address into the contents of the I2C Data register. 10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA signal. 11. If the I2C slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 12. If the slave does not acknowledge the first address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software respons to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore following steps). 12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register (2nd byte of address). 13. The I2C Controller shifts the second address byte out the SDA signal. After the first bit has been sent, the Transmit interrupt is asserted. 14. Software responds by setting the STOP bit in the I2C Control register. The TXI bit can be cleared at the same time. 15. Software polls the STOP bit of the I2C Control register. Hardware deasserts the STOP bit when the transaction is completed (STOP condition has been sent). 16. Software checks the ACK bit of the I2C Status register. If the slave acknowledged, the ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI interrupt do not occur because the STOP bit was set.
Write Transaction with a 10-Bit Address
Figure 31 illustrates the data transfer format for a 10-bit addressed slave. Shaded regions indicate data transferred from the I2C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I2C Controller.
Slave Address W=0 A 1st 7 bits Slave Address 2nd Byte
S
A Data A Data A/A P/S
Figure 31. 10-Bit Addressed Slave Data Transfer Format
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The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the read/write control bit (=0). The transmit operation is carried out in the same manner as 7bit addressing. The procedure for a transmit operation on a 10-bit addressed slave is as follows: 1. Software asserts the IEN bit in the I2C Control register. 2. Software asserts the TXI bit of the I2C Control register to enable Transmit interrupts. 3. The I2C interrupt asserts because the I2C Data register is empty. 4. Software responds to the TDRE interrupt by writing the first slave address byte to the I2C Data register. The least-significant bit must be 0 for the write operation. 5. Software asserts the START bit of the I2C Control register. 6. The I2C Controller sends the START condition to the I2C slave. 7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is asserted. 9. Software responds by writing the second byte of address into the contents of the I2C Data register. 10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA signal. 11. If the I2C slave acknowledges the first address byte by pulling the SDA signal low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 12. If the slave does not acknowledge the first address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 13. The I2C Controller shifts the second address byte out the SDA signal. After the first bit has been sent, the Transmit interrupt is asserted. 14. Software responds by writing a data byte to the I2C Data register. 15. The I2C Controller completes shifting the contents of the shift register on the SDA signal.
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16. If the I2C slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 17. If the slave does not acknowledge the second address byte or one of the data bytes, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 17. The I2C Controller shifts the data out by the SDA signal. After the first bit is sent, the Transmit interrupt is asserted. 18. If more bytes remain to be sent, return to step 14. 19. If the last byte is currently being sent, software sets the STOP bit of the I2C Control register (or START bit to initiate a new transaction). In the STOP case, software also clears the TXI bit of the I2C Control register at the same time. 20. The I2C Controller completes transmission of the last data byte on the SDA signal. 21. The slave may either Acknowledge or Not Acknowledge the last byte. Because either the STOP or START bit is already set, the NCKI interrupt does not occur. 22. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus and clears the STOP (or START) bit.
Read Transaction with a 7-Bit Address
Figure 32 illustrates the data transfer format for a read operation to a 7-bit addressed slave. The shaded regions indicate data transferred from the I2C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I2C Controller.
S Slave Address R=1 A Data A Data A P/S
Figure 32. Receive Data Transfer Format for a 7-Bit Addressed Slave
The procedure for a read operation to a 7-bit addressed slave is as follows: 1. Software writes the I2C Data register with a 7-bit slave address plus the read bit (=1). 2. Software asserts the START bit of the I2C Control register. 3. If this is a single byte transfer, Software asserts the NAK bit of the I2C Control register so that after the first byte of data has been read by the I2C Controller, a Not Acknowledge is sent to the I2C slave.
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4. The I2C Controller sends the START condition. 5. The I2C Controller shifts the address and read bit out the SDA signal. 6. If the I2C slave acknowledges the address by pulling the SDA signal Low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 7. If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is set in the Status register, ACK bit is cleared). Software responds to the Not Acknowledge interrupt by setting the STOP bit and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 7. The I2C Controller shifts in the byte of data from the I2C slave on the SDA signal. The I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last byte), else it sends an Acknowledge. 8. The I2C Controller asserts the Receive interrupt (RDRF bit set in the Status register). 9. Software responds by reading the I2C Data register which clears the RDRF bit. If there is only one more byte to receive, set the NAK bit of the I2C Control register. 10. If there are more bytes to transfer, return to step 7. 11. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C Controller. 12. Software responds by setting the STOP bit of the I2C Control register. 13. A STOP condition is sent to the I2C slave, the STOP and NCKI bits are cleared.
Read Transaction with a 10-Bit Address
Figure 33 illustrates the read transaction format for a 10-bit addressed slave. The shaded regions indicate data transferred from the I2C Controller to slaves and unshaded regions indicate data transferred from the slaves to the I2C Controller.
S Slave Address W=0 A 1st 7 bits Slave Address 2nd Byte AS Slave Address 1st 7 bits R=1 A Data A Data A P
Figure 33. Receive Data Format for a 10-Bit Addressed Slave
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the write control bit. The data transfer procedure for a read operation to a 10-bit addressed slave is as follows:
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1. Software writes 11110B followed by the two address bits and a 0 (write) to the I2C Data register. 2. Software asserts the START and TXI bits of the I2C Control register. 3. The I2C Controller sends the Start condition. 4. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register. 5. After the first bit has been shifted out, a Transmit interrupt is asserted. 6. Software responds by writing the lower eight bits of address to the I2C Data register. 7. The I2C Controller completes shifting of the two address bits and a 0 (write). 8. If the I2C slave acknowledges the first address byte by pulling the SDA signal low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 9. If the slave does not acknowledge the first address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore following steps). 9. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register (second address byte). 10. The I2C Controller shifts out the second address byte. After the first bit is shifted, the I2C Controller generates a Transmit interrupt. 11. Software responds by setting the START bit of the I2C Control register to generate a repeated START and by clearing the TXI bit. 12. Software responds by writing 11110B followed by the 2-bit slave address and a 1 (read) to the I2C Data register. 13. If only one byte is to be read, software sets the NAK bit of the I2C Control register. 14. After the I2C Controller shifts out the 2nd address byte, the I2C slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register. Continue with step 15. If the slave does not acknowledge the second address byte, the I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status register. Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 15. The I2C Controller sends the repeated START condition.
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16. The I2C Controller loads the I2C Shift register with the contents of the I2C Data register (third address transfer). 17. The I2C Controller sends 11110B followed by the two most significant bits of the slave read address and a 1 (read). 18. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next high period of SCL If the slave were to Not Acknowledge at this point (this should not happen because the slave did acknowledge the first two address bytes), software would respond by setting the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is complete (ignore the following steps). 19. The I2C Controller shifts in a byte of data from the I2C slave on the SDA signal. The I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last byte), else it sends an Acknowledge. 20. The I2C Controller asserts the Receive interrupt (RDRF bit set in the Status register). 21. Software responds by reading the I2C Data register which clears the RDRF bit. If there is only one more byte to receive, set the NAK bit of the I2C Control register. 22. If there are one or more bytes to transfer, return to step 19. 23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C Controller. 24. Software responds by setting the STOP bit of the I2C Control register. 25. A STOP condition is sent to the I2C slave and the STOP and NCKI bits are cleared.
I2C Control Register Definitions
I2C Data Register
The I2C Data register (Table 69) holds the data that is to be loaded into the I2C Shift register during a write to a slave. This register also holds data that is loaded from the I2C Shift
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register during a read from a slave. The I2C Shift Register is not accessible in the Register File address space, but is used only to buffer incoming and outgoing data.
Table 69. I2C Data Register (I2CDATA)
BITS FIELD RESET R/W ADDR
7
6
5
4
DATA 0 R/W F50H
3
2
1
0
I2C Status Register
The Read-only I2C Status register (Table 70) indicates the status of the I2C Controller.
Table 70. I2C Status Register (I2CSTAT)
BITS FIELD RESET R/W ADDR
7
TDRE 1
6
RDRF
5
ACK
4
10B
3
RD 0 R F51H
2
TAS
1
DSS
0
NCKI
TDRE--Transmit Data Register Empty When the I2C Controller is enabled, this bit is 1 when the I2C Data register is empty. When this bit is set, an interrupt is generated if the TXI bit is set, except when the I2C Controller is shifting in data during the reception of a byte or when shifting an address and the RD bit is set. This bit is cleared by writing to the I2CDATA register. RDRF--Receive Data Register Full This bit is set = 1 when the I2C Controller is enabled and the I2C Controller has received a byte of data. When asserted, this bit causes the I2C Controller to generate an interrupt. This bit is cleared by reading the I2C Data register (unless the read is performed using execution of the On-Chip Debugger's Read Register command). ACK--Acknowledge This bit indicates the status of the Acknowledge for the last byte transmitted or received. When set, this bit indicates that an Acknowledge occurred for the last byte transmitted or received. This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the
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last byte transmitted or received. It is not reset at the beginning of each transaction and is not reset when this register is read. Caution: Software must be cautious in making decisions based on this bit within a transaction because software cannot tell when the bit is updated by hardware. In the case of write transactions, the I2C pauses at the beginning of the Acknowledge cycle if the next transmit data or address byte has not been written (TDRE = 1) and STOP and START = 0. In this case the ACK bit is not updated until the transmit interrupt is serviced and the Acknowledge cycle for the previous byte completes. Refer to Address Only Transaction with a 7-bit Address on page 144 and Address Only Transaction with a 10-bit Address on page 146 for examples of how the ACK bit can be used.
10B--10-Bit Address This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit is set, if the five most-significant bits of the address are 11110B, this bit is set. When set, it is reset once the first byte of the address has been sent. RD--Read This bit indicates the direction of transfer of the data. It is active high during a read. The status of this bit is determined by the least-significant bit of the I2C Shift register after the START bit is set. TAS--Transmit Address State This bit is active high while the address is being shifted out of the I2C Shift register. DSS--Data Shift State This bit is active high while data is being shifted to or from the I2C Shift register. NCKI--NACK Interrupt This bit is set high when a Not Acknowledge condition is received or sent and neither the START nor the STOP bit is active. When set, this bit generates an interrupt that can only be cleared by setting the START or STOP bit, allowing the user to specify whether he wants to perform a STOP or a repeated START.
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I2C Control Register
The I2C Control register (Table 71) enables the I2C operation.
Table 71. I2C Control Register (I2CCTL)
BITS FIELD RESET R/W ADDR
7
IEN
6
START
5
STOP
4
BIRQ 0
3
TXI
2
NAK
1
FLUSH
0
FILTEN
R/W
R/W1
R/W1
R/W F52H
R/W
R/W1
W1
R/W
IEN--I2C Enable 1 = The I2C transmitter and receiver are enabled. 0 = The I2C transmitter and receiver are disabled. START--Send Start Condition This bit sends the Start condition. Once asserted, it is cleared by the I2C Controller after it sends the START condition or if the IEN bit is deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register. After this bit is set, the Start condition is sent if there is data in the I2C Data or I2C Shift register. If there is no data in one of these registers, the I2C Controller waits until the Data register is written. If this bit is set while the I2C Controller is shifting out data, it generates a START condition after the byte shifts and the acknowledge phase completes. If the STOP bit is also set, it also waits until the STOP condition is sent before the sending the START condition. STOP--Send Stop Condition This bit causes the I2C Controller to issue a Stop condition after the byte in the I2C Shift register has completed transmission or after a byte has been received in a receive operation. Once set, this bit is reset by the I2C Controller after a Stop condition has been sent or by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the register. BIRQ--Baud Rate Generator Interrupt Request This bit allows the I2C Controller to be used as an additional timer when the I2C Controller is disabled. This bit is ignored when the I2C Controller is enabled. 1 = An interrupt occurs every time the baud rate generator counts down to one. 0 = No baud rate generator interrupt occurs. TXI--Enable TDRE interrupts This bit enables the transmit interrupt when the I2C Data register is empty (TDRE = 1). 1 = Transmit interrupt (and DMA transmit request) is enabled. 0 = Transmit interrupt (and DMA transmit request) is disabled.
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NAK--Send NAK This bit sends a Not Acknowledge condition after the next byte of data has been read from the I2C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN bit is deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register. FLUSH--Flush Data Setting this bit to 1 clears the I2C Data register and sets the TDRE bit to 1. This bit allows flushing of the I2C Data register when a Not Acknowledge interrupt is received after the data has been sent to the I2C Data register. Reading this bit always returns 0. FILTEN--I2C Signal Filter Enable This bit enables low-pass digital filters on the SDA and SCL input signals. These filters reject any input pulse with periods less than a full system clock cycle. The filters introduce a 3-system clock cycle latency on the inputs. 1 = low-pass filters are enabled. 0 = low-pass filters are disabled.
I2C Baud Rate High and Low Byte Registers
The I2C Baud Rate High and Low Byte registers (Tables 72 and 73) combine to form a 16bit reload value, BRG[15:0], for the I2C Baud Rate Generator. When the I2C is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: 1. Disable the I2C by clearing the IEN bit in the I2C Control register to 0. 2. Load the desired 16-bit count value into the I2C Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the I2C Control register to 1. When configured as a general purpose timer, the interrupt interval is calculated using the following equation:
Interrupt Interval (s) = System Clock Period (s) xBRG[15:0] ]
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.
Table 72. I2C Baud Rate High Byte Register (I2CBRH)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRH FFH R/W F53H
3
2
1
0
BRH = I2C Baud Rate High Byte Most significant byte, BRG[15:8], of the I2C Baud Rate Generator's reload value. Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRH register returns the current value of the I2C Baud Rate Counter[15:8].
Table 73. I2C Baud Rate Low Byte Register (I2CBRL)
BITS FIELD RESET R/W ADDR
7
6
5
4
BRL FFH R/W F54H
3
2
1
0
BRL = I2C Baud Rate Low Byte Least significant byte, BRG[7:0], of the I2C Baud Rate Generator's reload value. Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRL register returns the current value of the I2C Baud Rate Counter[7:0].
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I2C Diagnostic State Register
The I2C Diagnostic State register (Table 74) provides observability of internal state. This is a read only register used for I2C diagnostics and manufacturing test.
Table 74. I2C Diagnostic State Register (I2CDST)
BITS FIELD RESET R/W ADDR
7
SCLIN X
6
SDAIN
5
STPCNT
4
3
2
TXRXSTATE 0
1
0
R F55H
SCLIN - Value of Serial Clock input signal SDAIN - Value of the Serial Data input signal STPCNT - Value of the internal Stop Count control signal TXRXSTATE - Value of the internal I2C state machine
TXRXSTATE 0_0000 0_0001 0_0010 0_0011 0_0100 0_0101 0_0110 0_0111 0_1000 0_1001 0_1010 0_1011 0_1100 0_1101 0_1110
State Description Idle State START State Send/Receive data bit 7 Send/Receive data bit 6 Send/Receive data bit 5 Send/Receive data bit 4 Send/Receive data bit 3 Send/Receive data bit 2 Send/Receive data bit 1 Send/Receive data bit 0 Data Acknowledge State Second half of data Acknowledge State used only for not acknowledge First part of STOP state Second part of STOP state 10-bit addressing: Acknowledge State for 2nd address byte 7-bit addressing: Address Acknowledge State
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TXRXSTATE 0_1111 1_0000 1_0001 1_0010 1_0011 1_0100 1_0101 1_0110 1_0111 1_1000 1_1001 1_1010 1_1011 1_1100 1_1101 1_1110 1_1111
State Description 10-bit address: Bit 0 (Least significant bit) of 2nd address byte 7-bit address: Bit 0 (Least significant bit) (R/W) of address byte 10-bit addressing: Bit 7 (Most significant bit) of 1st address byte 10-bit addressing: Bit 6 of 1st address byte 10-bit addressing: Bit 5 of 1st address byte 10-bit addressing: Bit 4 of 1st address byte 10-bit addressing: Bit 3 of 1st address byte 10-bit addressing: Bit 2 of 1st address byte 10-bit addressing: Bit 1 of 1st address byte 10-bit addressing: Bit 0 (R/W) of 1st address byte 10-bit addressing: Acknowledge state for 1st address byte 10-bit addressing: Bit 7 of 2nd address byte 7-bit addressing: Bit 7 of address byte 10-bit addressing: Bit 6 of 2nd address byte 7-bit addressing: Bit 6 of address byte 10-bit addressing: Bit 5 of 2nd address byte 7-bit addressing: Bit 5 of address byte 10-bit addressing: Bit 4 of 2nd address byte 7-bit addressing: Bit 4 of address byte 10-bit addressing: Bit 3 of 2nd address byte 7-bit addressing: Bit 3 of address byte 10-bit addressing: Bit 2 of 2nd address byte 7-bit addressing: Bit 2 of address byte 10-bit addressing: Bit 1 of 2nd address byte 7-bit addressing: Bit 1 of address byte
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I2C Diagnostic Control Register The I2C Diagnostic register (Table 75) provides control over diagnostic modes. This register is a read/write register used for I2C diagnostics.
Table 75. I2C Diagnostic Control Register (I2CDIAG)
BITS FIELD RESET R/W ADDR
7
6
5
4
Reserved 0 R F56H
3
2
1
0
DIAG
R/W
DIAG = Diagnostic Control Bit - Selects read back value of the Baud Rate Reload registers. 0 = Normal mode. Reading the Baud Rate High and Low Byte registers returns the baud rate reload value. 1 = Diagnostic mode. Reading the Baud Rate High and Low Byte registers returns the baud rate counter value.
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Direct Memory Access Controller
Overview
The 64K Series Direct Memory Access (DMA) Controller provides three independent Direct Memory Access channels. Two of the channels (DMA0 and DMA1) transfer data between the on-chip peripherals and the Register File. The third channel (DMA_ADC) controls the Analog-to-Digital Converter (ADC) operation and transfers SINGLE-SHOT mode ADC output data to the Register File.
Operation
DMA0 and DMA1 Operation
DMA0 and DMA1, referred to collectively as DMAx, transfer data either from the on-chip peripheral control registers to the Register File, or from the Register File to the on-chip peripheral control registers. The sequence of operations in a DMAx data transfer is: 1. DMAx trigger source requests a DMA data transfer. 2. DMAx requests control of the system bus (address and data) from the eZ8 CPU. 3. After the eZ8 CPU acknowledges the bus request, DMAx transfers either a single byte or a two-byte word (depending upon configuration) and then returns system bus control back to the eZ8 CPU. 4. If Current Address equals End Address: - DMAx reloads the original Start Address - If configured to generate an interrupt, DMAx sends an interrupt request to the Interrupt Controller - If configured for single-pass operation, DMAx resets the DEN bit in the DMAx Control register to 0 and the DMA is disabled. If Current Address does not equal End Address, the Current Address increments by 1 (single-byte transfer) or 2 (two-byte word transfer).
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Configuring DMA0 and DMA1 for Data Transfer
Follow these steps to configure and enable DMA0 or DMA1: 1. Write to the DMAx I/O Address register to set the Register File address identifying the on-chip peripheral control register. The upper nibble of the 12-bit address for on-chip peripheral control registers is always FH. The full address is {FH, DMAx_IO[7:0]} 2. Determine the 12-bit Start and End Register File addresses. The 12-bit Start Address is given by {DMAx_H[3:0], DMA_START[7:0]}. The 12-bit End Address is given by {DMAx_H[7:4], DMA_END[7:0]}. 3. Write the Start and End Register File address high nibbles to the DMAx End/Start Address High Nibble register. 4. Write the lower byte of the Start Address to the DMAx Start/Current Address register. 5. Write the lower byte of the End Address to the DMAx End Address register. 6. Write to the DMAx Control register to complete the following: - Select loop or single-pass mode operation - Select the data transfer direction (either from the Register File RAM to the onchip peripheral control register; or from the on-chip peripheral control register to the Register File RAM) - Enable the DMAx interrupt request, if desired - Select Word or Byte mode - Select the DMAx request trigger - Enable the DMAx channel
DMA_ADC Operation
DMA_ADC transfers data from the ADC to the Register File. The sequence of operations in a DMA_ADC data transfer is: 1. ADC completes conversion on the current ADC input channel and signals the DMA controller that two-bytes of ADC data are ready for transfer. 2. DMA_ADC requests control of the system bus (address and data) from the eZ8 CPU. 3. After the eZ8 CPU acknowledges the bus request, DMA_ADC transfers the two-byte ADC output value to the Register File and then returns system bus control back to the eZ8 CPU. 4. If the current ADC Analog Input is the highest numbered input to be converted: - DMA_ADC resets the ADC Analog Input number to 0 and initiates data conversion on ADC Analog Input 0. - If configured to generate an interrupt, DMA_ADC sends an interrupt request to the Interrupt Controller
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If the current ADC Analog Input is not the highest numbered input to be converted, DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input.
Configuring DMA_ADC for Data Transfer
Follow these steps to configure and enable DMA_ADC: 1. Write the DMA_ADC Address register with the 7 most-significant bits of the Register File address for data transfers. 2. Write to the DMA_ADC Control register to complete the following: - Enable the DMA_ADC interrupt request, if desired - Select the number of ADC Analog Inputs to convert - Enable the DMA_ADC channel Caution: When using the DMA_ADC to perform conversions on multiple ADC inputs, the Analog-to-Digital Converter must be configured for SINGLESHOT mode. If the ADC_IN field in the DMA_ADC Control Register is greater than 000b, the ADC must be in SINGLE-SHOT mode. CONTINUOUS mode operation of the ADC can only be used in conjunction with DMA_ADC if the ADC_IN field in the DMA_ADC Control Register is reset to 000b to enable conversion on ADC Analog Input 0 only.
DMA Control Register Definitions
DMAx Control Register
The DMAx Control register (Table 76) enables and selects the mode of operation for DMAx.
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Table 76. DMAx Control Register (DMAxCTL)
BITS FIELD RESET R/W ADDR
7
DEN
6
DLE
5
DDIR
4
IRQEN 0 R/W
3
WSEL
2
1
RSS
0
FB0H, FB8H
DEN--DMAx Enable 0 = DMAx is disabled and data transfer requests are disregarded. 1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger source. DLE--DMAx Loop Enable 0 = DMAx reloads the original Start Address and is then disabled after the End Address data is transferred. 1 = DMAx, after the End Address data is transferred, reloads the original Start Address and continues operating. DDIR--DMAx Data Transfer Direction 0 = Register File on-chip peripheral control register. 1 = on-chip peripheral control register Register File. IRQEN--DMAx Interrupt Enable 0 = DMAx does not generate any interrupts. 1 = DMAx generates an interrupt when the End Address data is transferred. WSEL--Word Select 0 = DMAx transfers a single byte per request. 1 = DMAx transfers a two-byte word per request. The address for the on-chip peripheral control register must be an even address. RSS--Request Trigger Source Select The Request Trigger Source Select field determines the peripheral that can initiate a DMA transfer. The corresponding interrupts do not need to be enabled within the Interrupt Controller to initiate a DMA transfer. However, if the Request Trigger Source can enable or disable the interrupt request sent to the Interrupt Controller, the interrupt request must be enabled within the Request Trigger Source block. 000 = Timer 0. 001 = Timer 1. 010 = Timer 2. 011 = Timer 3. 100 = DMA0 Control register: UART0 Received Data register contains valid data. DMA1 Control register: UART0 Transmit Data register empty.
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101 = DMA0 Control register: UART1 Received Data register contains valid data. DMA1 Control register: UART1 Transmit Data register empty. 110 = DMA0 Control register: I2C Receiver Interrupt. DMA1 Control register: I2C Transmitter Interrupt register empty. 111 = Reserved.
DMAx I/O Address Register
The DMAx I/O Address register (Table 77) contains the low byte of the on-chip peripheral address for data transfer. The full 12-bit Register File address is given by {FH, DMAx_IO[7:0]}. When the DMA is configured for two-byte word transfers, the DMAx I/ O Address register must contain an even numbered address.
Table 77. DMAx I/O Address Register (DMAxIO)
BITS FIELD RESET R/W ADDR
7
6
5
4
DMA_IO X R/W
3
2
1
0
FB1H, FB9H
DMA_IO--DMA on-chip peripheral control register address This byte sets the low byte of the on-chip peripheral control register address on Register File Page FH (addresses F00H to FFFH).
DMAx Address High Nibble Register
The DMAx Address High register (Table 78) specifies the upper four bits of address for the Start/Current and End Addresses of DMAx.
Table 78. DMAx Address High Nibble Register (DMAxH)
BITS FIELD RESET R/W ADDR
7
6
5
4
3
2
1
0
DMA_END_H X R/W FB2H, FBAH
DMA_START_H
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DMA_END_H--DMAx End Address High Nibble These bits, used with the DMAx End Address Low register, form a 12-bit End Address. The full 12-bit address is given by {DMA_END_H[3:0], DMA_END[7:0]}. DMA_START_H--DMAx Start/Current Address High Nibble These bits, used with the DMAx Start/Current Address Low register, form a 12-bit Start/ Current Address. The full 12-bit address is given by {DMA_START_H[3:0], DMA_START[7:0]}.
DMAx Start/Current Address Low Byte Register
The DMAx Start/Current Address Low register, in conjunction with the DMAx Address High Nibble register, forms a 12-bit Start/Current Address. Writes to this register set the Start Address for DMA operations. Each time the DMA completes a data transfer, the 12bit Start/Current Address increments by either 1 (single-byte transfer) or 2 (two-byte word transfer). Reads from this register return the low byte of the Current Address to be used for the next DMA data transfer.
Table 79. DMAx Start/Current Address Low Byte Register (DMAxSTART)
BITS FIELD RESET R/W ADDR
7
6
5
4
3
2
1
0
DMA_START X R/W FB3H, FBBH
DMA_START--DMAx Start/Current Address Low These bits, with the four lower bits of the DMAx_H register, form the 12-bit Start/Current address. The full 12-bit address is given by {DMA_START_H[3:0], DMA_START[7:0]}.
DMAx End Address Low Byte Register
The DMAx End Address Low Byte register (Table 79), in conjunction with the DMAx_H register (Table 80), forms a 12-bit End Address.
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Table 80. DMAx End Address Low Byte Register (DMAxEND)
BITS FIELD RESET R/W ADDR
7
6
5
4
3
2
1
0
DMA_END X R/W FB4H, FBCH
DMA_END--DMAx End Address Low These bits, with the four upper bits of the DMAx_H register, form a 12-bit address. This address is the ending location of the DMAx transfer. The full 12-bit address is given by {DMA_END_H[3:0], DMA_END[7:0]}.
DMA_ADC Address Register
The DMA_ADC Address register (Table 82) points to a block of the Register File to store ADC conversion values as illustrated in Table 81. This register contains the seven mostsignificant bits of the 12-bit Register File addresses. The five least-significant bits are calculated from the ADC Analog Input number (5-bit base address is equal to twice the ADC Analog Input number). The 10-bit ADC conversion data is stored as two bytes with the most significant byte of the ADC data stored at the even numbered Register File address. Table 81 provides an example of the Register File addresses if the DMA_ADC Address register contains the value 72H.
Table 81. DMA_ADC Register File Address Example ADC Analog Input 0 1 2 3 4 5 6 7 8 Register File Address (Hex)1 720H-721H 722H-723H 724H-725H 726H-727H 728H-729H 72AH-72BH 72CH-72DH 72EH-72FH 730H-731H
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Table 81. DMA_ADC Register File Address Example ADC Analog Input 9 10 11
1
Register File Address (Hex)1 732H-733H 734H-735H 736H-737H
DMAA_ADDR set to 72H.
Table 82. DMA_ADC Address Register (DMAA_ADDR)
BITS FIELD RESET R/W ADDR
7
6
5
4
DMAA_ADDR X R/W FBDH
3
2
1
0
Reserved
DMAA_ADDR--DMA_ADC Address These bits specify the seven most-significant bits of the 12-bit Register File addresses used for storing the ADC output data. The ADC Analog Input Number defines the five least-significant bits of the Register File address. Full 12-bit address is {DMAA_ADDR[7:1], 4-bit ADC Analog Input Number, 0}. Reserved This bit is reserved and must be 0.
DMA_ADC Control Register
The DMA_ADC Control register (Table 83) enables and sets options (DMA enable and interrupt enable) for ADC operation.
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Table 83. DMA_ADC Control Register (DMAACTL)
BITS FIELD RESET R/W ADDR
7
DAEN
6
IRQEN
5
Reserved
4
3
2
ADC_IN
1
0
0 R/W FBEH
DAEN--DMA_ADC Enable 0 = DMA_ADC is disabled and the ADC Analog Input Number (ADC_IN) is reset to 0. 1 = DMA_ADC is enabled. IRQEN--Interrupt Enable 0 = DMA_ADC does not generate any interrupts. 1 = DMA_ADC generates an interrupt after transferring data from the last ADC Analog Input specified by the ADC_IN field. Reserved These bits are reserved and must be 0. ADC_IN--ADC Analog Input Number These bits set the number of ADC Analog Inputs to be used in the continuous update (data conversion followed by DMA data transfer). The conversion always begins with ADC Analog Input 0 and then progresses sequentially through the other selected ADC Analog Inputs. 0000 = ADC Analog Input 0 updated. 0001 = ADC Analog Inputs 0-1 updated. 0010 = ADC Analog Inputs 0-2 updated. 0011 = ADC Analog Inputs 0-3 updated. 0100 = ADC Analog Inputs 0-4 updated. 0101 = ADC Analog Inputs 0-5 updated. 0110 = ADC Analog Inputs 0-6 updated. 0111 = ADC Analog Inputs 0-7 updated. 1000 = ADC Analog Inputs 0-8 updated. 1001 = ADC Analog Inputs 0-9 updated. 1010 = ADC Analog Inputs 0-10 updated. 1011 = ADC Analog Inputs 0-11 updated. 1100-1111 = Reserved.
DMA Status Register
The DMA Status register (Table 84) indicates the DMA channel that generated the interrupt and the ADC Analog Input that is currently undergoing conversion. Reads from this register reset the Interrupt Request Indicator bits (IRQA, IRQ1, and IRQ0) to 0. There-
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fore, software interrupt service routines that read this register must process all three interrupt sources from the DMA.
Table 84. DMA_ADC Status Register (DMAA_STAT)
BITS FIELD RESET R/W ADDR
7
6
CADC[3:0]
5
4
3
Reserved 0 R FBFH
2
IRQA
1
IRQ1
0
IRQ0
CADC[3:0]--Current ADC Analog Input This field identifies the Analog Input that the ADC is currently converting. Reserved This bit is reserved and must be 0. IRQA--DMA_ADC Interrupt Request Indicator This bit is automatically reset to 0 each time a read from this register occurs. 0 = DMA_ADC is not the source of the interrupt from the DMA Controller. 1 = DMA_ADC completed transfer of data from the last ADC Analog Input and generated an interrupt. IRQ1--DMA1 Interrupt Request Indicator This bit is automatically reset to 0 each time a read from this register occurs. 0 = DMA1 is not the source of the interrupt from the DMA Controller. 1 = DMA1 completed transfer of data to/from the End Address and generated an interrupt. IRQ0--DMA0 Interrupt Request Indicator This bit is automatically reset to 0 each time a read from this register occurs. 0 = DMA0 is not the source of the interrupt from the DMA Controller. 1 = DMA0 completed transfer of data to/from the End Address and generated an interrupt.
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Analog-to-Digital Converter
Overview
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary number. The features of the sigma-delta ADC include:
* * * *
12 analog input sources are multiplexed with general-purpose I/O ports Interrupt upon conversion complete Internal voltage reference generator Direct Memory Access (DMA) controller can automatically initiate data conversion and transfer of the data from 1 to 12 of the analog inputs
Architecture
Figure 34 illustrates the three major functional blocks (converter, analog multiplexer, and voltage reference generator) of the ADC. The ADC converts an analog input signal to its digital representation. The 12-input analog multiplexer selects one of the 12 analog input sources. The ADC requires an input reference voltage for the conversion. The voltage reference for the conversion may be input through the external VREF pin or generated internally by the voltage reference generator.
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VREF Internal Voltage Reference Generator
Analog Input Multiplexer ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 ANA8 ANA9 ANA10 ANA11
Analog-to-Digital Converter
Reference Input
Analog Input
ANAIN[3:0]
Figure 34. Analog-to-Digital Converter Block Diagram
The sigma-delta ADC architecture provides alias and image attenuation below the amplitude resolution of the ADC in the frequency range of DC to one-half the ADC clock rate (one-fourth the system clock rate). The ADC provides alias free conversion for frequencies up to one-half the ADC clock rate. Thus the sigma-delta ADC exhibits high noise immunity making it ideal for embedded applications. In addition, monotonicity (no missing codes) is guaranteed by design.
Operation
Automatic Power-Down
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles, portions of the ADC are automatically powered-down. From this power-down state, the ADC requires 40 system clock cycles to power-up. The ADC powers up when a conversion is requested using the ADC Control register.
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Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital conversion on the selected analog input channel. After completion of the conversion, the ADC shuts down. The steps for setting up the ADC and initiating a single-shot conversion are as follows: 1. Enable the desired analog inputs by configuring the general-purpose I/O pins for alternate function. This configuration disables the digital input and output drivers. 2. Write to the ADC Control register to configure the ADC and begin the conversion. The bit fields in the ADC Control register can be written simultaneously: - Write to the ANAIN[3:0] field to select one of the 12 analog input sources. - Clear CONT to 0 to select a single-shot conversion. - Write to the VREF bit to enable or disable the internal voltage reference generator. - Set CEN to 1 to start the conversion. 3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires 5129 system clock cycles to complete. If a single-shot conversion is requested from an ADC powered-down state, the ADC uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. 4. When the conversion is complete, the ADC control logic performs the following operations: - 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}. - CEN resets to 0 to indicate the conversion is complete. - An interrupt request is sent to the Interrupt Controller. 5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically powered-down.
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analogto-digital conversion on the selected analog input. Each new data value over-writes the previous value stored in the ADC Data registers. An interrupt is generated after each conversion. Caution: In CONTINUOUS mode, users must be aware that ADC updates are limited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at the input are not seen at the next output from the ADC. The response of the ADC (in all modes) is limited by the input signal bandwidth and the latency.
The steps for setting up the ADC and initiating continuous conversion are as follows:
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1. Enable the desired analog input by configuring the general-purpose I/O pins for alternate function. This disables the digital input and output driver. 2. Write to the ADC Control register to configure the ADC for continuous conversion. The bit fields in the ADC Control register may be written simultaneously: - Write to the ANAIN[3:0] field to select one of the 12 analog input sources. - Set CONT to 1 to select continuous conversion. - Write to the VREF bit to enable or disable the internal voltage reference generator. - Set CEN to 1 to start the conversions. 3. When the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic performs the following operations: - CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all subsequent conversions in continuous operation. - An interrupt request is sent to the Interrupt Controller to indicate the conversion is complete. 4. Thereafter, the ADC writes a new 10-bit data result to {ADCD_H[7:0], ADCD_L[7:6]} every 256 system clock cycles. An interrupt request is sent to the Interrupt Controller when each conversion is complete. 5. To disable continuous conversion, clear the CONT bit in the ADC Control register to 0.
DMA Control of the ADC
The Direct Memory Access (DMA) Controller can control operation of the ADC including analog input selection and conversion enable. For more information on the DMA and configuring for ADC operations refer to the chapter Direct Memory Access Controller on page 161.
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ADC Control Register Definitions
ADC Control Register
The ADC Control register selects the analog input channel and initiates the analog-to-digital conversion.
Table 85. ADC Control Register (ADCCTL)
BITS FIELD RESET R/W ADDR
7
CEN 0
6
Reserved
5
VREF 1
4
CONT
3
2
1
0
ANAIN[3:0] 0 R/W F70H
CEN--Conversion Enable 0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears this bit to 0 when a conversion has been completed. 1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already in progress, the conversion restarts. This bit remains 1 until the conversion is complete. Reserved--Must be 0. VREF 0 = Internal voltage reference generator enabled. The VREF pin should be left unconnected (or capacitively coupled to analog ground) if the internal voltage reference is selected as the ADC reference voltage. 1 = Internal voltage reference generator disabled. An external voltage reference must be provided through the VREF pin. CONT 0 = Single-shot conversion. ADC data is output once at completion of the 5129 system clock cycles. 1 = Continuous conversion. ADC data updated every 256 system clock cycles. ANAIN--Analog Input Select These bits select the analog input for conversion. Not all Port pins in this list are available in all packages for the Z8F642x familyZ8R642x family of products. Refer to the Signal and Pin Descriptions chapter for information regarding the Port pins available with each package style. Do not enable unavailable analog inputs. 0000 = ANA0 0001 = ANA1 0010 = ANA2 0011 = ANA3
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0100 = ANA4 0101 = ANA5 0110 = ANA6 0111 = ANA7 1000 = ANA8 1001 = ANA9 1010 = ANA10 1011 = ANA11 11XX = Reserved.
ADC Data High Byte Register
The ADC Data High Byte register (Table 86) contains the upper eight bits of the 10-bit ADC output. During a single-shot conversion, this value is invalid. Access to the ADC Data High Byte register is read-only. The full 10-bit ADC result is given by {ADCD_H[7:0], ADCD_L[7:6]}. Reading the ADC Data High Byte register latches data in the ADC Low Bits register
.
Table 86. ADC Data High Byte Register (ADCD_H)
BITS FIELD RESET R/W ADDR
7
6
5
4
ADCD_H X R F72H
3
2
1
0
ADCD_H--ADC Data High Byte This byte contains the upper eight bits of the 10-bit ADC output. These bits are not valid during a single-shot conversion. During a continuous conversion, the last conversion output is held in this register. These bits are undefined after a Reset.
ADC Data Low Bits Register
The ADC Data Low Bits register (Table 87) contains the lower two bits of the conversion value. The data in the ADC Data Low Bits register is latched each time the ADC Data High Byte register is read. Reading this register always returns the lower two bits of the conversion last read into the ADC High Byte register. Access to the ADC Data Low Bits
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register is read-only. The full 10-bit ADC result is given by {ADCD_H[7:0], ADCD_L[7:6]}.
Table 87. ADC Data Low Bits Register (ADCD_L)
BITS FIELD RESET R/W ADDR
7
ADCD_L
6
5
4
3
Reserved X R F73H
2
1
0
ADCD_L--ADC Data Low Bits These are the least significant two bits of the 10-bit ADC output. These bits are undefined after a Reset. Reserved These bits are reserved and are always undefined.
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Flash Memory
Overview
The products in the Z8 Encore!(R) 64K Series feature up to 64KB (65,536 bytes) of nonvolatile Flash memory with read/write/erase capability. The Flash memory can be programmed and erased in-circuit by either user code or through the On-Chip Debugger. The Flash memory array is arranged in 512-byte per page. The 512-byte page is the minimum Flash block size that can be erased. The Flash memory is also divided into 8 sectors which can be protected from programming and erase operations on a per sector basis. Table 88 describes the Flash memory configuration for each device in the 64K Series. Table 89 lists the sector address ranges. Figure 35 illustrates the Flash memory arrangement.
Table 88. Flash Memory Configurations Number of Pages 32 48 64 96 128 Flash Memory Addresses 0000H - 3FFFH 0000H - 5FFFH 0000H - 7FFFH 0000H - BFFFH 0000H - FFFFH Number of Sectors 8 6 8 6 8 Pages per Sector 4 8 8 16 16
Part Number Z8F162x Z8F242x Z8F322x Z8F482x Z8F642x
Flash Size 16K (16,384) 24K (24,576) 32K (32,768) 48K (49,152) 64K (65,536)
Sector Size 2K (2048) 4K (4096) 4K (4096) 8K (8192) 8K (8192)
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Table 89. Flash Memory Sector Addresses Flash Sector Address Ranges Sector Number 0 1 2 3 4 5 6 7 Z8F162x 0000H-07FFH 0800H-0FFFH 1000H-17FFH 1800H-1FFFH 2000H-27FFH 2800H-2FFFH 3000H-37FFH 3800H-3FFFH Z8F242x 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH 4000H-4FFFH 5000H-5FFFH N/A N/A Z8F322x 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH 4000H-4FFFH 5000H-5FFFH 6000H-6FFFH 7000H-7FFFH Z8F482x 0000H-1FFFH 2000H-3FFFH 4000H-5FFFH 6000H-7FFFH 8000H-9FFFH A000H-BFFFH N/A N/A Z8F642x 0000H-1FFFH 2000H-3FFFH 4000H-5FFFH 6000H-7FFFH 8000H-9FFFH A000H-BFFFH C000H-DFFFH E000H-FFFFH
64KB Flash Program Memory Addresses FFFFH FE00H FDFFH FC00H FBFFH FA00H
128 Pages 512 Bytes per Page
05FFH 0400H 03FFH 0200H 01FFH 0000H
Figure 35. Flash Memory Arrangement
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Information Area
Table 90 describes the 64K Series Information Area. This 512-byte Information Area is accessed by setting bit 7 of the Page Select Register to 1. When access is enabled, the Information Area is mapped into Flash Memory and overlays the 512 bytes at addresses FE00H to FFFFH. When the Information Area access is enabled, LDC instructions return data from the Information Area. CPU instruction fetches always comes from Flash Memory regardless of the Information Area access bit. Access to the Information Area is readonly.
Table 90. 64K Series Information Area Map Flash Memory Address (Hex) FE00H-FE3FH FE40H-FE53H Function Reserved Part Number 20-character ASCII alphanumeric code Left justified and filled with zeros Reserved
FE54H-FFFFH
Operation
The Flash Controller provides the proper signals and timing for Byte Programming, Page Erase, and Mass Erase of the Flash memory. The Flash Controller contains a protection mechanism, via the Flash Control register (FCTL), to prevent accidental programming or erasure. The following subsections provide details on the various operations (Lock, Unlock, Sector Protect, Byte Programming, Page Erase, and Mass Erase).
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Timing Using the Flash Frequency Registers
Before performing a program or erase operation on the Flash memory, the user must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency registers allow programming and erasure of the Flash with system clock frequencies ranging from 20kHz through 20MHz (the valid range is limited to the device operating frequencies). The Flash Frequency High and Low Byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash Frequency value must contain the system clock frequency in KHz. This value is calculated using the following equation:.
System Clock Frequency (Hz) FFREQ[15:0] = --------------------------------------------------------------------------1000
Caution: Flash programming and erasure are not supported for system clock frequencies below 20KHz, above 20MHz, or outside of the device operating frequency range. The Flash Frequency High and Low Byte registers must be loaded with the correct value to insure proper Flash programming and erase operations.
Flash Read Protection
The user code contained within the Flash memory can be protected from external access. Programming the Flash Read Protect Option Bit prevents reading of user code by the OnChip Debugger or by using the Flash Controller Bypass mode. Refer to the Option Bits chapter and the On-Chip Debugger chapter for more information.
Flash Write/Erase Protection
The 64K Series provides several levels of protection against accidental program and erasure of the Flash memory contents. This protection is provided by the Flash Controller unlock mechanism, the Flash Sector Protect register, and the Flash Write Protect option bit. Flash Controller Unlock Mechanism At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash memory. To program or erase the Flash memory, the Flash controller must be unlocked. After unlocking the Flash Controller, the Flash can be programmed or erased. Any value written by user code to the Flash Control register or Page Select Register out of sequence will lock the Flash Controller. The proper steps to unlock the Flash Controller from user code are: 1. Write 00H to the Flash Control register to reset the Flash Controller.
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2. Write the page to be programmed or erased to the Page Select register. 3. Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register. 5. Re-write the page written in step 2 to the Page Select register. Flash Sector Protection The Flash Sector Protect register can be configured to prevent sectors from being programmed or erased. Once a sector is protected, it cannot be unprotected by user code. The Flash Sector Protect register is cleared after reset and any previously written protection values is lost. User code must write this register in their initialization routine if they want to enable sector protection. The Flash Sector Protect register shares its Register File address with the Page Select register. The Flash Sector Protect register is accessed by writing the Flash Control register with 5EH. Once the Flash Sector Protect register is selected, it can be accessed at the Page Select Register address. When user code writes the Flash Sector Protect register, bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register write operations. Writing a value other than 5EH to the Flash Control register de-selects the Flash Sector Protect register and re-enables access to the Page Select register. The steps to setup the Flash Sector Protect register from user code are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write 5EH to the Flash Control register to select the Flash Sector Protect register. 3. Read and/or write the Flash Sector Protect register which is now at Register File address FF9H. 4. Write 00H to the Flash Control register to return the Flash Controller to its reset state. Flash Write Protection Option Bit The Flash Write Protect option bit can be enabled to block all program and erase operations from user code. Refer to the Option Bits chapter for more information.
Byte Programming
When the Flash Controller is unlocked, writes to Flash Memory from user code will program a byte into the Flash if the address is located in the unlocked page. An erased Flash byte contains all ones (FFH). The programming operation can only be used to change bits from one to zero. To change a Flash bit (or multiple bits) from zero to one requires a Page Erase or Mass Erase operation. Byte Programming can be accomplished using the eZ8 CPU's LDC or LDCI instructions. Refer to the eZ8 CPU User Manual for a description of the LDC and LDCI instructions.
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While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. Interrupts that occur when a Programming operation is in progress are serviced once the Programming operation is complete. To exit Programming mode and lock the Flash Controller, write 00H to the Flash Control register. User code cannot program Flash Memory on a page that lies in a protected sector. When user code writes memory locations, only addresses located in the unlocked page are programmed. Memory writes outside of the unlocked page are ignored. Caution: Each memory location must not be programmed more than twice before an erase occurs.
The proper steps to program the Flash from user code are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write the page of memory to be programmed to the Page Select register. 3. Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register. 5. Re-write the page written in step 2 to the Page Select register. 6. Write Flash Memory using LDC or LDCI instructions to program the Flash. 7. Repeat step 6 to program additional memory locations on the same page. 8. Write 00H to the Flash Control register to lock the Flash Controller.
Page Erase
The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash memory sets all bytes in that page to the value FFH. The Page Select register identifies the page to be erased. While the Flash Controller executes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase operation completes. Interrupts that occur when the Page Erase operation is in progress are serviced once the Page Erase operation is complete. When the Page Erase operation is complete, the Flash Controller returns to its locked state. Only pages located in unprotected sectors can be erased. The proper steps to perform a Page Erase operation are: 1. Write 00H to the Flash Control register to reset the Flash Controller. 2. Write the page to be erased to the Page Select register. 3. Write the first unlock command 73H to the Flash Control register. 4. Write the second unlock command 8CH to the Flash Control register.
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5. Re-write the page written in step 2 to the Page Select register. 6. Write the Page Erase command 95H to the Flash Control register.
Mass Erase
The Flash memory cannot be Mass Erased by user code.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins. Bypassing the Flash Controller allows faster Programming algorithms by controlling the Flash programming signals directly. Flash Controller Bypass is recommended for gang programming applications and large volume customers who do not require in-circuit programming of the Flash memory. Refer to the document entitled Third-Party Flash Programming Support for Z8 Encore!(R) for more information on bypassing the Flash Controller. This document is available for download at www.zilog.com.
Flash Controller Behavior in Debug Mode
The following changes in behavior of the Flash Controller occur when the Flash Controller is accessed using the On-Chip Debugger:
* * * * * * *
Caution:
The Flash Write Protect option bit is ignored. The Flash Sector Protect register is ignored for programming and erase operations. Programming operations are not limited to the page selected in the Page Select register. Bits in the Flash Sector Protect register can be written to one or zero. The second write of the Page Select register to unlock the Flash Controller is not necessary. The Page Select register can be written when the Flash Controller is unlocked. The Mass Erase command is enabled through the Flash Control register. For security reasons, flash controller allows only a single page to be opened for write/erase. When writing multiple flash pages, the flash controller must go through the unlock sequence again to select another page.
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Flash Control Register Definitions
Flash Control Register
The Flash Control register (Table 91) unlocks the Flash Controller for programming and erase operations, or to select the Flash Sector Protect register. The Write-only Flash Control Register shares its Register File address with the Read-only Flash Status Register.
Table 91. Flash Control Register (FCTL)
BITS FIELD RESET R/W ADDR
7
6
5
4
FCMD 0 W FF8H
3
2
1
0
FCMD--Flash Command 73H = First unlock command. 8CH = Second unlock command. 95H = Page erase command. 63H = Mass erase command 5EH = Flash Sector Protect register select. * All other commands, or any command out of sequence, lock the Flash Controller.
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Flash Status Register
The Flash Status register (Table 92) indicates the current state of the Flash Controller. This register can be read at any time. The Read-only Flash Status Register shares its Register File address with the Write-only Flash Control Register.
Table 92. Flash Status Register (FSTAT)
BITS FIELD RESET R/W ADDR
7
Reserved
6
5
4
3
FSTAT 0 R FF8H
2
1
0
Reserved These bits are reserved and must be 0. FSTAT--Flash Controller Status 00_0000 = Flash Controller locked 00_0001 = First unlock command received 00_0010 = Second unlock command received 00_0011 = Flash Controller unlocked 00_0100 = Flash Sector Protect register selected 00_1xxx = Program operation in progress 01_0xxx = Page erase operation in progress 10_0xxx = Mass erase operation in progress
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Page Select Register
The Page Select (FPS) register (Table 93) selects one of the 128 available Flash memory pages to be erased or programmed. Each Flash Page contains 512 bytes of Flash memory. During a Page Erase operation, all Flash memory locations with the 7 most significant bits of the address given by the PAGE field are erased to FFH. The Page Select register shares its Register File address with the Flash Sector Protect Register. The Page Select register cannot be accessed when the Flash Sector Protect register is enabled.
Table 93. Page Select Register (FPS)
BITS FIELD RESET R/W ADDR
7
INFO_EN
6
5
4
3
PAGE 0 R/W FF9H
2
1
0
INFO_EN--Information Area Enable 0 = Information Area is not selected. 1 = Information Area is selected. The Information area is mapped into the Flash Memory address space at addresses FE00H through FFFFH. PAGE--Page Select This 7-bit field selects the Flash memory page for Programming and Page Erase operations. Flash Memory Address[15:9] = PAGE[6:0].
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Flash Sector Protect Register
The Flash Sector Protect register (Table 94) protects Flash memory sectors from being programmed or erased from user code. The Flash Sector Protect register shares its Register File address with the Page Select register. The Flash Sector protect register can be accessed only after writing the Flash Control register with 5EH. User code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code).
Table 94. Flash Sector Protect Register (FPROT)
BITS FIELD RESET R/W ADDR
7
SECT7
6
SECT6
5
SECT5
4
SECT4 0 R/W1 FF9H
3
SECT3
2
SECT2
1
SECT1
0
SECT0
R/W1 = Register is accessible for Read operations. Register can be written to 1 only (via user code).
SECTn--Sector Protect 0 = Sector n can be programmed or erased from user code. 1 = Sector n is protected and cannot be programmed or erased from user code. * User code can only write bits from 0 to 1.
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Flash Frequency High and Low Byte Registers
The Flash Frequency High and Low Byte registers (Tables 95 and 96) combine to form a 16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash Frequency registers must be written with the system clock frequency in KHz for Program and Erase operations. Calculate the Flash Frequency value using the following equation:
System Clock Frequency FFREQ[15:0] = { FFREQH[7:0],FFREQL[7:0] } = -------------------------------------------------------------1000
Caution:
Flash programming and erasure is not supported for system clock frequencies below 20KHz, above 20MHz, or outside of the valid operating frequency range for the device. The Flash Frequency High and Low Byte registers must be loaded with the correct value to insure proper program and erase times.
Table 95. Flash Frequency High Byte Register (FFREQH)
BITS FIELD RESET R/W ADDR
7
6
5
4
FFREQH 0 R/W FFAH
3
2
1
0
Table 96. Flash Frequency Low Byte Register (FFREQL)
BITS FIELD RESET R/W ADDR
7
6
5
4
FFREQL 0 R/W FFBH
3
2
1
0
FFREQH and FFREQL--Flash Frequency High and Low Bytes These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value.
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Option Bits
Overview
Option Bits allow user configuration of certain aspects of the 64K Series operation. The feature configuration data is stored in the Flash Memory and read during Reset. The features available for control via the Option Bits are:
* * * * * *
Watch-Dog Timer time-out response selection-interrupt or Reset. Watch-Dog Timer enabled at Reset. The ability to prevent unwanted read access to user code in Flash Memory. The ability to prevent accidental programming and erasure of the user code in Flash Memory. Voltage Brown-Out configuration-always enabled or disabled during STOP mode to reduce STOP mode power consumption. Oscillator mode selection-for high, medium, and low power crystal oscillators, or external RC oscillator.
Operation
Option Bit Configuration By Reset
Each time the Option Bits are programmed or erased, the device must be Reset for the change to take place. During any reset operation (System Reset, Reset, or STOP Mode Recovery), the Option Bits are automatically read from the Flash Memory and written to Option Configuration registers. The Option Configuration registers control operation of the devices within the 64K Series. Option Bit control is established before the device exits Reset and the eZ8 CPU begins code execution. The Option Configuration registers are not part of the Register File and are not accessible for read or write access.
Option Bit Address Space
The first two bytes of Flash Memory at addresses 0000H (Table 97) and 0001H (Table 98) are reserved for the user Option Bits. The byte at Flash Memory address 0000H configures user options. The byte at Flash Memory address 0001H is reserved for future use and must remain unprogrammed.
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Flash Memory Address 0000H
Table 97. Flash Option Bits At Flash Memory Address 0000H
BITS
7
6
5
4
3
VBO_AO U R/W
2
RP
1
Reserved
0
FWP
FIELD WDT_RES WDT_AO RESET R/W ADDR
OSC_SEL[1:0]
Program Memory 0000H
Note: U = Unchanged by Reset. R/W = Read/Write.
WDT_RES--Watch-Dog Timer Reset 0 = Watch-Dog Timer time-out generates an interrupt request. Interrupts must be globally enabled for the eZ8 CPU to acknowledge the interrupt request. 1 = Watch-Dog Timer time-out causes a Short Reset. This setting is the default for unprogrammed (erased) Flash. WDT_AO--Watch-Dog Timer Always On 0 = Watch-Dog Timer is automatically enabled upon application of system power. WatchDog Timer can not be disabled except during STOP Mode (if configured to power down during STOP Mode). 1 = Watch-Dog Timer is enabled upon execution of the WDT instruction. Once enabled, the Watch-Dog Timer can only be disabled by a Reset or STOP Mode Recovery. This setting is the default for unprogrammed (erased) Flash. OSC_SEL[1:0]--Oscillator Mode Selection 00 = On-chip oscillator configured for use with external RC networks (<4MHz). 01 = Minimum power for use with very low frequency crystals (32KHz to 1.0MHz). 10 = Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz to 10.0MHz). 11 = Maximum power for use with high frequency crystals (8.0MHz to 20.0MHz). This setting is the default for unprogrammed (erased) Flash. VBO_AO--Voltage Brown-Out Protection Always On 0 = Voltage Brown-Out Protection is disabled in STOP mode to reduce total power consumption. 1 = Voltage Brown-Out Protection is always enabled including during STOP mode. This setting is the default for unprogrammed (erased) Flash. RP--Read Protect 0 = User program code is inaccessible. Limited control features are available through the On-Chip Debugger.
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1 = User program code is accessible. All On-Chip Debugger commands are enabled. This setting is the default for unprogrammed (erased) Flash. Reserved These Option Bits are reserved for future use and must always be 1.This setting is the default for unprogrammed (erased) Flash. FWP--Flash Write Protect (Flash version only)
FWP 0 1 Description Programming, Page Erase, and Mass Erase through User Code is disabled. Mass Erase is available through the On-Chip Debugger. Programming, and Page Erase are enabled for all of Flash Program Memory.
Flash Memory Address 0001H
Table 98. Options Bits at Flash Memory Address 0001H
BITS FIELD RESET R/W ADDR
7
6
5
4
Reserved U R/W
3
2
1
0
Program Memory 0001H
Note: U = Unchanged by Reset. R = Read-Only. R/W = Read/Write.
Reserved These Option Bits are reserved for future use and must always be 1. This setting is the default for unprogrammed (erased) Flash.
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On-Chip Debugger
Overview
The 64K Series products contain an integrated On-Chip Debugger (OCD) that provides advanced debugging features including:
* * * * Architecture
Reading and writing of the Register File Reading and writing of Program and Data Memory Setting of Breakpoints Execution of eZ8 CPU instructions
The On-Chip Debugger consists of four primary functional blocks: transmitter, receiver, auto-baud generator, and debug controller. Figure 36 illustrates the architecture of the OnChip Debugger
System Clock
Auto-Baud Detector/Generator
eZ8 CPU Control
Transmitter Debug Controller DBG Pin Receiver
Figure 36. On-Chip Debugger Block Diagram
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Operation
OCD Interface
The On-Chip Debugger uses the DBG pin for communication with an external host. This one-pin interface is a bi-directional open-drain interface that transmits and receives data. Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously. The serial data on the DBG pin is sent using the standard asynchronous data format defined in RS-232. This pin can interface the 64K Series products to the serial port of a host PC using minimal external hardware.Two different methods for connecting the DBG pin to an RS-232 interface are depicted in Figures 37 and 38. Caution: For operation of the On-Chip Debugger, all power pins (VDD and AVDD) must be supplied with power, and all ground pins (VSS and AVSS) must be properly grounded. The DBG pin is open-drain and must always be connected to VDD through an external pull-up resistor to ensure proper operation.
VDD RS-232 Transceiver Diode RS-232 TX DBG Pin
10K Ohm
RS-232 RX
Figure 37. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (1)
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VDD RS-232 Transceiver RS-232 TX
Open-Drain Buffer
10K Ohm DBG Pin
RS-232 RX
Figure 38. Interfacing the On-Chip Debugger's DBG Pin with an RS-232 Interface (2)
Debug Mode
The operating characteristics of the 64K Series devices in DEBUG mode are:
* * * * *
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute specific instructions. The system clock operates unless in STOP mode. All enabled on-chip peripherals operate unless in STOP mode. Automatically exits HALT mode. Constantly refreshes the Watch-Dog Timer, if enabled.
Entering Debug Mode The device enters DEBUG mode following any of the following operations:
* * *
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface. eZ8 CPU execution of a BRK (Breakpoint) instruction (when enabled). If the DBG pin is Low when the device exits Reset, the On-Chip Debugger automatically puts the device into DEBUG mode.
Exiting Debug Mode The device exits DEBUG mode following any of the following operations:
* * *
Clearing the DBGMODE bit in the OCD Control Register to 0. Power-on reset Voltage Brown Out reset
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* *
Asserting the RESET pin Low to initiate a Reset. Driving the DBG pin Low while the device is in STOP mode initiates a System Reset.
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit (Figure 39).
START D0 D1 D2 D3 D4 D5 D6 D7 STOP
Figure 39. OCD Data Format
OCD Auto-Baud Detector/Generator
To run over a range of baud rates (bits per second) with various system clock frequencies, the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD is idle until it receives data. The OCD requires that the first character sent from the host is the character 80H. The character 80H has eight continuous bits Low (one Start bit plus 7 data bits). The Auto-Baud Detector measures this period and sets the OCD Baud Rate Generator accordingly. The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud rate is the system clock frequency divided by 512. For optimal operation, the maximum recommended baud rate is the system clock frequency divided by 8. The theoretical maximum baud rate is the system clock frequency divided by 4. This theoretical maximum is possible for low noise designs with clean signals. Table 99 lists minimum and recommended maximum baud rates for sample crystal frequencies.
Table 99. OCD Baud-Rate Limits System Clock Frequency (MHz) 20.0 1.0 0.032768 (32KHz) Recommended Maximum Baud Rate (kbits/s) 2500 125.0 4.096 Minimum Baud Rate (kbits/s) 39.1 1.96 0.064
If the OCD receives a Serial Break (nine or more continuous bits Low) the Auto-Baud Detector/Generator resets. The Auto-Baud Detector/Generator can then be reconfigured by sending 80H.
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OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
* * *
Serial Break (a minimum of nine continuous bits Low) Framing Error (received Stop bit is Low) Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress, transmits a Serial Break 4096 system clock cycles long back to the host, and resets the Auto-Baud Detector/Generator. A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD. Because of the open-drain nature of the interface, returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early. The host transmits a Serial Break on the DBG pin when first connecting to the 64K Series devices or when recovering from an error. A Serial Break from the host resets the AutoBaud Generator/Detector but does not reset the OCD Control register. A Serial Break leaves the device in DEBUG mode if that is the current mode. The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High. Because of the opendrain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD is transmitting a character.
Breakpoints
Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are enabled, the OCD idles the eZ8 CPU and enters DEBUG mode. If Breakpoints are not enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP. If breakpoints are enabled, the OCD can be configured to automatically enter DEBUG mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK instruction, then the CPU is still enabled to service DMA and interrupt requests. The loop on BRK instruction can be used to service interrupts in the background. For interrupts to be serviced in the background, there cannot be any breakpoints in the interrupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine. For interrupts to be serviced in the background, interrupts must also be enabled. Debugging software should not automatically enable interrupts when using this feature, since interrupts are typically disabled during critical sections of code where interrupts should not occur (such as adjusting the stack pointer or modifying shared data). Software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is looping on a BRK instruction. When software wants to stop the CPU on the BRK instruction it is looping on, software should not set the DBGMODE bit of the OCDCTL register. The CPU may have vectored to and be in the middle of an interrupt service routine when this bit gets set. Instead, software must clear the BRKLP bit. This action allows the CPU to
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finish the interrupt service routine it may be in and return the BRK instruction. When the CPU returns to the BRK instruction it was previously looping on, it automatically sets the DBGMODE bit and enter DEBUG mode. Software detects that the majority of the OCD commands are still disabled when the eZ8 CPU is looping on a BRK instruction. The eZ8 CPU must be stopped and the part must be in DEBUG mode before these commands can be issued. Breakpoints in Flash Memory The BRK instruction is opcode 00H, which corresponds to the fully programmed state of a byte in Flash memory. To implement a Breakpoint, write 00H to the desired address, overwriting the current instruction. To remove a Breakpoint, the corresponding page of Flash memory must be erased and reprogrammed with the original data.
On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the DBG interface. During normal operation, only a subset of the OCD commands are available. In DEBUG mode, all OCD commands become available unless the user code and control registers are protected by programming the Read Protect Option Bit (RP). The Read Protect Option Bit prevents the code in memory from being read out of the 64K Series products. When this option is enabled, several of the OCD commands are disabled. Table 100 contains a summary of the On-Chip Debugger commands. Each OCD command is described in further detail in the bulleted list following Table 100. Table 100 indicates those commands that operate when the device is not in DEBUG mode (normal operation) and those commands that are disabled by programming the Read Protect Option Bit.
Table 100. On-Chip Debugger Commands Enabled when NOT in DEBUG mode? Yes Yes Yes Yes Disabled by Read Protect Option Bit Cannot clear DBGMODE bit Disabled Disabled
Debug Command Read OCD Revision Read OCD Status Register Read Runtime Counter Write OCD Control Register Read OCD Control Register Write Program Counter Read Program Counter
Command Byte 00H 02H 03H 04H 05H 06H 07H
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Table 100. On-Chip Debugger Commands (Continued) Enabled when NOT in DEBUG mode? Disabled by Read Protect Option Bit Only writes of the Flash Memory Control registers are allowed. Additionally, only the Mass Erase command is allowed to be written to the Flash Control register. DisabledDisabled Disabled Disabled Disabled Disabled Disabled Disabled -
Debug Command Write Register
Command Byte 08H
Read Register Write Program Memory Read Program Memory Write Data Memory Read Data Memory Read Program Memory CRC Reserved Step Instruction Stuff Instruction Execute Instruction Reserved
09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H - FFH
-
In the following bulleted list of OCD Commands, data and commands sent from the host to the On-Chip Debugger are identified by 'DBG Command/Data'. Data sent from the On-Chip Debugger back to the host is identified by 'DBG Data'
*
Read OCD Revision (00H)--The Read OCD Revision command determines the version of the On-Chip Debugger. If OCD commands are added, removed, or changed, this revision number changes.
DBG 00H DBG OCDREV[15:8] (Major revision number) DBG OCDREV[7:0] (Minor revision number)
*
Read OCD Status Register (02H)--The Read OCD Status Register command reads the OCDSTAT register.
DBG 02H DBG OCDSTAT[7:0]
*
Write OCD Control Register (04H)--The Write OCD Control Register command writes the data that follows to the OCDCTL register. When the Read Protect Option Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0 and the only method of putting the device back into normal operating mode is to reset the device.
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DBG 04H DBG OCDCTL[7:0]
*
Read OCD Control Register (05H)--The Read OCD Control Register command reads the value of the OCDCTL register.
DBG 05H DBG OCDCTL[7:0]
*
Write Program Counter (06H)--The Write Program Counter command writes the data that follows to the eZ8 CPU's Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the Program Counter (PC) values are discarded.
DBG 06H DBG ProgramCounter[15:8] DBG ProgramCounter[7:0]
*
Read Program Counter (07H)--The Read Program Counter command reads the value in the eZ8 CPU's Program Counter (PC). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFFFH.
DBG 07H DBG ProgramCounter[15:8] DBG ProgramCounter[7:0]
*
Write Register (08H)--The Write Register command writes data to the Register File. Data can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). If the device is not in DEBUG mode, the address and data values are discarded. If the Read Protect Option Bit is enabled, then only writes to the Flash Control Registers are allowed and all other register write data values are discarded.
DBG DBG DBG DBG DBG 08H {4'h0,Register Address[11:8]} Register Address[7:0] Size[7:0] 1-256 data bytes
*
Read Register (09H)--The Read Register command reads data from the Register File. Data can be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFH for all the data values.
DBG DBG DBG DBG DBG 09H {4'h0,Register Address[11:8] Register Address[7:0] Size[7:0] 1-256 data bytes
*
Write Program Memory (0AH)--The Write Program Memory command writes data to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). The on-chip Flash Controller must be written to and unlocked for the
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programming operation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the data is discarded.
DBG DBG DBG DBG DBG DBG 0AH Program Memory Address[15:8] Program Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Read Program Memory (0BH)--The Read Program Memory command reads data from Program Memory. This command is equivalent to the LDC and LDCI instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, this command returns FFH for the data.
DBG DBG DBG DBG DBG DBG 0BH Program Memory Address[15:8] Program Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Write Data Memory (0CH)--The Write Data Memory command writes data to Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the data is discarded.
DBG DBG DBG DBG DBG DBG 0CH Data Memory Address[15:8] Data Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Read Data Memory (0DH)--The Read Data Memory command reads from Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the device is not in DEBUG mode, this command returns FFH for the data.
DBG DBG DBG DBG DBG DBG 0DH Data Memory Address[15:8] Data Memory Address[7:0] Size[15:8] Size[7:0] 1-65536 data bytes
*
Read Program Memory CRC (0EH)--The Read Program Memory CRC command computes and returns the CRC (cyclic redundancy check) of Program Memory using
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the 16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this command returns FFFFH for the CRC value. Unlike most other OCD Read commands, there is a delay from issuing of the command until the OCD returns the data. The OCD reads the Program Memory, calculates the CRC value, and returns the result. The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory.
DBG 0EH DBG CRC[15:8] DBG CRC[7:0]
*
Step Instruction (10H)--The Step Instruction command steps one assembly instruction at the current Program Counter (PC) location. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command.
DBG 10H
*
Stuff Instruction (11H)--The Stuff Instruction command steps one assembly instruction and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the instruction are read from Program Memory. This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command.
DBG 11H DBG opcode[7:0]
*
Execute Instruction (12H)--The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU. This command can also step over Breakpoints. The number of bytes to send for the instruction depends on the opcode. If the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this command
DBG 12H DBG 1-5 byte opcode
On-Chip Debugger Control Register Definitions
OCD Control Register
The OCD Control register (Table 101) controls the state of the On-Chip Debugger. This register enters or exits DEBUG mode and enables the BRK instruction. It can also reset the Z8F642x familyZ8R642x family device.
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A "reset and stop" function can be achieved by writing 81H to this register. A "reset and go" function can be achieved by writing 41H to this register. If the device is in DEBUG mode, a "run" function can be implemented by writing 40H to this register.
Table 101. OCD Control Register (OCDCTL)
BITS
7
6
BRKEN
5
4
3
2
1
Reserved
0
RST
FIELD DBGMODE RESET R/W
DBGACK BRKLOOP 0
R/W
R
R/W
DBGMODE--Debug Mode Setting this bit to 1 causes the device to enter DEBUG mode. When in DEBUG mode, the eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to start running again. This bit is automatically set when a BRK instruction is decoded and Breakpoints are enabled. If the Read Protect Option Bit is enabled, this bit can only be cleared by resetting the device, it cannot be written to 0. 0 = The 64K Series device is operating in Normal mode. 1 = The 64K Series device is in DEBUG mode. BRKEN--Breakpoint Enable This bit controls the behavior of the BRK instruction (opcode 00H). By default, Breakpoints are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit. 0 = BRK instruction is disabled. 1 = BRK instruction is enabled. DBGACK--Debug Acknowledge This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends an Debug Acknowledge character (FFH) to the host when a Breakpoint occurs. 0 = Debug Acknowledge is disabled. 1 = Debug Acknowledge is enabled. BRKLOOP--Breakpoint Loop This bit determines what action the OCD takes when a BRK instruction is decoded if breakpoints are enabled (BRKEN is 1). If this bit is 0, then the DBGMODE bit is automatically set to 1 and the OCD entered DEBUG mode. If BRKLOOP is set to 1, then the eZ8 CPU loops on the BRK instruction. 0 = BRK instruction sets DBGMODE to 1. 1 = eZ8 CPU loops on BRK instruction. Reserved These bits are reserved and must be 0.
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RST--Reset Setting this bit to 1 resets the 64K Series devices. The devices go through a normal PowerOn Reset sequence with the exception that the On-Chip Debugger is not reset. This bit is automatically cleared to 0 when the reset finishes. 0 = No effect 1 = Reset the 64K Series device
OCD Status Register
The OCD Status register (Table 102) reports status information about the current state of the debugger and the system.
Table 102. OCD Status Register (OCDSTAT)
BITS FIELD RESET R/W
7
IDLE
6
HALT
5
RPEN
4
3
2
Reserved
1
0
0 R
IDLE--CPU idling This bit is set if the part is in DEBUG mode (DBGMODE is 1), or if a BRK instruction occurred since the last time OCDCTL was written. This can be used to determine if the CPU is running or if it is idling. 0 = The eZ8 CPU is running. 1 = The eZ8 CPU is either stopped or looping on a BRK instruction. HALT--HALT Mode 0 = The device is not in HALT mode. 1 = The device is in HALT mode. RPEN--Read Protect Option Bit Enabled 0 = The Read Protect Option Bit is disabled (1). 1 = The Read Protect Option Bit is enabled (0), disabling many OCD commands. Reserved These bits are always 0.
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On-Chip Oscillator
Overview
The products in the 64K Series feature an on-chip oscillator for use with external crystals with frequencies from 32KHz to 20MHz. In addition, the oscillator can support external RC networks with oscillation frequencies up to 4MHz or ceramic resonators with oscillation frequencies up to 20MHz. This oscillator generates the primary system clock for the internal eZ8 CPU and the majority of the on-chip peripherals. Alternatively, the XIN input pin can also accept a CMOS-level clock input signal (32KHz-20MHz). If an external clock generator is used, the XOUT pin must be left unconnected. When configured for use with crystal oscillators or external clock drivers, the frequency of the signal on the XIN input pin determines the frequency of the system clock (that is, no internal clock divider). In RC operation, the system clock is driven by a clock divider (divide by 2) to ensure 50% duty cycle.
Operating Modes
The 64K Series products support 4 different oscillator modes:
* * * *
On-chip oscillator configured for use with external RC networks (<4MHz). Minimum power for use with very low frequency crystals (32KHz to 1.0MHz). Medium power for use with medium frequency crystals or ceramic resonators (0.5MHz to 10.0MHz). Maximum power for use with high frequency crystals or ceramic resonators (8.0MHz to 20.0MHz).
The oscillator mode is selected through user-programmable Option Bits. Refer to the Option Bits chapter for information.
Crystal Oscillator Operation
Figure 40 illustrates a recommended configuration for connection with an external fundamental-mode, parallel-resonant crystal operating at 20MHz. Recommended 20MHz crystal specifications are provided in Table 103. Resistor R1 is optional and limits total power dissipation by the crystal. The printed circuit board layout must add no more than 4pF of
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stray capacitance to either the XIN or XOUT pins. If oscillation does not occur, reduce the values of capacitors C1 and C2 to decrease loading.
On-Chip Oscillator
XIN
XOUT
R1 = 220 Crystal
C1 = 22pF
C2 = 22pF
Figure 40. Recommended 20MHz Crystal Oscillator Configuration
Table 103. Recommended Crystal Oscillator Specifications (20MHz Operation) Parameter Frequency Resonance Mode Series Resistance (RS) Load Capacitance (CL) Shunt Capacitance (C0) Drive Level Value 20 Parallel Fundamental 25 20 7 1 pF pF mW Maximum Maximum Maximum Maximum Units MHz Comments
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Oscillator Operation with an External RC Network
The External RC oscillator mode is applicable to timing insensitive applications. Figure 41 illustrates a recommended configuration for connection with an external resistor-capacitor (RC) network.
VDD
R
XIN
C
Figure 41. Connecting the On-Chip Oscillator to an External RC Network
An external resistance value of 45k is recommended for oscillator operation with an external RC network. The minimum resistance value to ensure operation is 40k. The typical oscillator frequency can be estimated from the values of the resistor (R in k) and capacitor (C in pF) elements using the following equation:
1 x10 Oscillator Frequency (kHz) = -------------------------------------------------------( 0.4 x R x C ) + ( 4 x C )
Figure 42 illustrates the typical (3.3V and 250C) oscillator frequency as a function of the capacitor (C in pF) employed in the RC network assuming a 45k external resistor. For very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed circuit board should be included in the estimation of the oscillator frequency. It is possible to operate the RC oscillator using only the parasitic capacitance of the package and printed circuit board. To minimize sensitivity to external parasitics, external capacitance values in excess of 20pF are recommended.
6
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4000 3750 3500 3250 3000 2750 2500 Frequency (kHz) 2250 2000 1750 1500 1250 1000 750 500 250 0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 C (pF)
Figure 42. Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45k Resistor
Caution:
When using the external RC oscillator mode, the oscillator may stop oscillating if the power supply drops below 2.7V, but before the power supply drops to the voltage brown-out threshold. The oscillator will resume oscillation as soon as the supply voltage exceeds 2.7V.
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Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in Table 104 may cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs must be tied to one of the supply voltages (VDD or VSS).
Table 104. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage on any pin with respect to VSS Voltage on VDD pin with respect to VSS Maximum current on input and/or inactive output pin Maximum output current from active output pin 80-Pin QFP Maximum Ratings at -40C to 70C Total power dissipation Maximum current into VDD or out of VSS 80-Pin QFP Maximum Ratings at 70C to 125C Total power dissipation Maximum current into VDD or out of VSS 68-Pin PLCC Maximum Ratings at -40C to 70C Total power dissipation Maximum current into VDD or out of VSS 68-Pin PLCC Maximum Ratings at 700C to 1250C
Notes: 1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H), RESET, and where noted otherwise.
Minimum Maximum -40 -65 -0.3 -0.3 -5 -25 +125 +150 +5.5 +3.6 +5 +25
Units C C V V A mA
Notes
1
550 150
mW mA
200 56
mW mA
1000 275
mW mA
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Table 104. Absolute Maximum Ratings (Continued) Parameter Total power dissipation Maximum current into VDD or out of VSS 64-Pin LQFP Maximum Ratings at -40C to 70C Total power dissipation Maximum current into VDD or out of VSS 64-Pin LQFP Maximum Ratings at 700C to 1250C Total power dissipation Maximum current into VDD or out of VSS 44-Pin PLCC Maximum Ratings at -40C to 70C Total power dissipation Maximum current into VDD or out of VSS 44-Pin PLCC Maximum Ratings at 700C to 1250C Total power dissipation Maximum current into VDD or out of VSS 44-pin LQFP Maximum Ratings at -40C to 70C Total power dissipation Maximum current into VDD or out of VSS 44-pin LQFP Maximum Ratings at 700C to 1250C Total power dissipation Maximum current into VDD or out of VSS 40-pin PDIP Maximum Ratings at -40C to 70C Total power dissipation Maximum current into VDD or out of VSS 40-pin PDIP Maximum Ratings at 700C to 1250C Total power dissipation Maximum current into VDD or out of VSS 540 150 mW mA 1000 275 mW mA 360 100 mW mA 750 200 mW mA 295 83 mW mA 750 200 mW mA 540 150 mW mA 1000 275 mW mA Minimum Maximum 500 140 Units mW mA Notes
Notes: 1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H), RESET, and where noted otherwise.
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DC Characteristics
Table 105 lists the DC characteristics of the 64K Series products. All voltages are referenced to VSS, the primary system ground.
Table 105. DC Characteristics TA = -400C to 1250C Symbol Parameter VDD VIL1 VIL2 VIH1 VIH2 VIH3 VOL1 VOH1 VOL2 Supply Voltage Low Level Input Voltage Low Level Input Voltage High Level Input Voltage High Level Input Voltage High Level Input Voltage Low Level Output Voltage Standard Drive High Level Output Voltage Standard Drive Low Level Output Voltage High Drive High Level Output Voltage High Drive Low Level Output Voltage High Drive High Level Output Voltage High Drive RAM Data Retention Input Leakage Current Tri-State Leakage Current GPIO Port Pad Capacitance XIN Pad Capacitance Minimum Typical Maximum Units Conditions 3.0 -0.3 -0.3 0.7*VDD 0.7*VDD 0.8*VDD - 2.4 - - - - - - - - - - 3.6 0.3*VDD 0.2*VDD 5.5 VDD+0.3 VDD+0.3 0.4 - 0.6 V V V V V V V V V For all input pins except RESET, DBG, XIN For RESET, DBG, and XIN. Port A, C, D, E, F, and G pins. Port B and H pins. RESET, DBG, and XIN pins IOL = 2mA; VDD = 3.0V High Output Drive disabled. IOH = -2mA; VDD = 3.0V High Output Drive disabled. IOL = 20mA; VDD = 3.3V High Output Drive enabled TA = -400C to +700C IOH = -20mA; VDD = 3.3V High Output Drive enabled; TA = -400C to +700C IOL = 15mA; VDD = 3.3V High Output Drive enabled; TA = +700C to +1050C IOH = 15mA; VDD = 3.3V High Output Drive enabled; TA = +700C to +1050C
VOH2
2.4
-
-
V
VOL3
-
-
0.6
V
VOH3
2.4
-
-
V
VRAM IIL ITL CPAD CXIN
0.7 -5 -5 - -
- - - 8.02 8.0
2
- +5 +5 - -
V A VDD = 3.6V; VIN = VDD or VSS1 A VDD = 3.6V pF pF
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Table 105. DC Characteristics (Continued) TA = -400C to 1250C Symbol Parameter CXOUT XOUT Pad Capacitance IPU IDDA Weak Pull-up Current Active Mode Supply Current (See Figures 43 and 44) GPIO pins configured as outputs Halt Mode Supply Current (See Figures 45 and 46) GPIO pins configured as outputs Stop Mode Supply Current (See Figures 47 and 48) GPIO pins configured as outputs Minimum Typical Maximum Units Conditions - 30 - - 9.52 100 11 9 4 - - 3 520 - 350 16 12 11 9 7 5 5 4 700 650 - 10 25 pF A VDD = 3.0 - 3.6 V mA VDD = 3.6 V, Fsysclk = 20 MHz VDD = 3.3 V mA VDD = 3.6 V, Fsysclk = 10 MHz VDD = 3.3 V mA VDD = 3.6 V, Fsysclk = 20 MHz VDD = 3.3 V mA VDD = 3.6 V, Fsysclk = 10 MHz VDD = 3.3 V A VDD = 3.6 V, VBO and WDT Enabled VDD = 3.3 V A VDD = 3.6 V, TA = 0 to 700 VBO Disabled WDT Enabled VDD = 3.3 V A VDD = 3.6 V, TA = -40 to +1050 VBO Disabled WDT Enabled VDD = 3.3 V A VDD = 3.6 V, TA = -40 to +1250 VBO Disabled WDT Enabled VDD = 3.3 V
IDDH
IDDS
20 - 80
70 - 250
150
1 2
This condition excludes all pins that have on-chip pull-ups, when driven Low. These values are provided for design guidance only and are not tested in production.
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Figure 43 illustrates the typical active mode current consumption while operating at 25C versus the system clock frequency. All GPIO pins are configured as outputs and driven High.
stics
15 12
Idd (mA)
9 6 3 0 0 5 10 15 20
System Clock Frequency (MHz)
3.0V
3.3V
3.6V
Figure 43. Typical Active Mode Idd Versus System Clock Frequency
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Figure 44 illustrates the maximum active mode current consumption across the full operating temperature range of the device and versus the system clock frequency. All GPIO pins are configured as outputs and driven High.
stics
15 12
Idd (mA)
9 6 3 0 0 5 10 15 20 System Clock Frequency (MHz) 3.0V 3.3V 3.6V
Figure 44. Maximum Active Mode Idd Versus System Clock Frequency
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Figure 45 illustrates the typical current consumption in HALT mode while operating at 25C versus the system clock frequency. All GPIO pins are configured as outputs and driven High.
5 4 HALT Idd (mA) 3 2 1 0 0 5 10 15 20 System Clock Frequency (MHz) 3.0V 3.3V 3.6V
Figure 45. Typical HALT Mode Idd Versus System Clock Frequency
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Figure 45 illustrates the maximum HALT mode current consumption across the full operating temperature range of the device and versus the system clock frequency. All GPIO pins are configured as outputs and driven High.
6 5
Halt Idd (mA)
4 3 2 1 0 0 5 10 15 20 System Clock Frequency (MHz) 3.0V 3.3V 3.6V
Figure 46. Maximum HALT Mode Icc Versus System Clock Frequency
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Figure 47 illustrates the maximum current consumption in STOP mode with the VBO and Watch-Dog Timer enabled versus the power supply voltage. All GPIO pins are configured as outputs and driven High.
700
STOP Idd (microamperes)
650 600 550 500 450 400 3.0 3.2
Vdd (V)
3.4
3.6
-40/105C
0/70C
25C Typical
Figure 47. Maximum STOP Mode Idd with VBO enabled versus Power Supply Voltage
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Figure 48 illustrates the maximum current consumption in STOP mode with the VBO disabled and Watch-Dog Timer enabled versus the power supply voltage. All GPIO pins are configured as outputs and driven High. Disabling the Watch-Dog Timer and its internal RC oscillator in STOP mode will provide some additional reduction in STOP mode current consumption. This small current reduction would be indistinquishable on the scale of Figure 48.
120.00 100.00 STOP Idd (microamperes) 80.00 60.00 40.00 20.00 0.00 3.0 3.2 Vdd (V) 25C Typical 0/70C -40/105C -40/+125C 3.4 3.6
Figure 48. Maximum STOP Mode Idd with VBO Disabled versus Power Supply Voltage
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On-Chip Peripheral AC and DC Electrical Characteristics
Table 106. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing TA = -400C to 1250C Symbol Parameter VPOR VVBO Power-On Reset Voltage Threshold Voltage Brown-Out Reset Voltage Threshold VPOR to VVBO hysteresis Starting VDD voltage to ensure valid Power-On Reset. TANA TPOR Power-On Reset Analog Delay Power-On Reset Digital Delay Voltage Brown-Out Pulse Rejection Period Minimum Typical1 Maximum 2.40 2.30 50 - 2.70 2.60 100 VSS 2.90 2.85 - - Units V V mV V Conditions VDD = VPOR VDD = VVBO
- -
50 6.6
- -
s ms
VDD > VPOR; TPOR Digital Reset delay follows TANA 66 WDT Oscillator cycles (10KHz) + 16 System Clock cycles (20MHz) VDD < VVBO to generate a Reset.
TVBO
- 0.10
10 -
- 100
s ms
TRAMP Time for VDD to transition from VSS to VPOR to ensure valid Reset
1 Data in the typical column is from characterization at 3.3V and 00C. These values are provided for design guidance only and are not tested in production.
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Table 107. External RC Oscillator Electrical Characteristics and Timing TA = -400C to 1250C Symbol Parameter VDD REXT CEXT FOSC Operating Voltage Range External Resistance from XIN to VDD External Capacitance from XIN to VSS External RC Oscillation Frequency Minimum Typical1 Maximum 2.70 40 0 -
1
Units V k pF MHz
Conditions
- 45 20 -
- 200 1000 4
VDD = VVBO
1 When using the external RC oscillator mode, the oscillator may stop oscillating if the power supply drops below 2.7V, but before the power supply drops to the voltage brown-out threshold. The oscillator will resume oscillation as soon as the supply voltage exceeds 2.7V.
Table 108. Reset and STOP Mode Recovery Pin Timing TA = -400C to 1250C Symbol Parameter TRESET RESET pin assertion to initiate a System Reset. TSMR STOP Mode Recovery pin Pulse Rejection Period Minimum Typical Maximum 4 10 - 20 - 40 Units TCLK ns Conditions Not in STOP Mode. TCLK = System Clock period. RESET, DBG, and GPIO pins configured as SMR sources.
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Table 109 list the Flash Memory electrical characteristics and timing.
Table 109. Flash Memory Electrical Characteristics and Timing VDD = 3.0 - 3.6V TA = -400C to 1250C Parameter Flash Byte Read Time Flash Byte Program Time Flash Page Erase Time Flash Mass Erase Time Writes to Single Address Before Next Erase Flash Row Program Time Minimum Typical 50 20 10 200 - - - - - - - - Maximum - 40 - - 2 8 ms Cumulative program time for single row cannot exceed limit before next erase. This parameter is only an issue when bypassing the Flash Controller. 250C Units ns s ms ms Notes
Data Retention Endurance, -40 to 1050C Endurance, 1060 to 1250C
100 10,000 1,000
- - -
- - -
years
cycles Program / erase cycles cycles Program / erase cycles
Table 110 lists the Watch-Dog Timer electrical characteristics and timing.
Table 110. Watch-Dog Timer Electrical Characteristics and Timing VDD = 3.0 - 3.6V TA = -400C to 1250C Symbol FWDT IWDT Parameter WDT Oscillator Frequency WDT Oscillator Current including internal RC oscillator Minimum Typical 5 - 10 <1 Maximum 20 5 Units kHz A Conditions
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Table 111 provides electrical characteristics and timing information for the Analog-to-Digital Converter. Figure 49 illustrates the input frequency response of the ADC.
Table 111. Analog-to-Digital Converter Electrical Characteristics and Timing VDD = 3.0 - 3.6V TA = -400C to 1250C Symbol Parameter Resolution Differential Nonlinearity (DNL) Integral Nonlinearity (INL) DC Offset Error DC Offset Error Minimum Typical 10 -.25 -3.0 -35 -50 +1.0 - - - Maximum - +.25 3.0 25 25 Units bits lsb lsb mV mV 44-pin LQFP, 44-pin PLCC, and 68-pin PLCC packages. VDD = 3.0 - 3.6V TA = -400C to 1050C Conditions External VREF = 3.0V; Guaranteed by design External VREF = 3.0V
VREF VCREF TCREF
Internal Reference Voltage Voltage Coefficient of Internal Reference Voltage Temperature Coefficient of Internal Reference Voltage Single-Shot Conversion Period Continuous Conversion Period
1.9 - - - - -
2.0 78 1 5129 256 - 150
2.4 - - - - 150
V
mV/V VREF variation as a function of AVDD. mV/0C cycles System clock cycles cycles System clock cycles k Recommended
RS Zin VREF
Analog Source Impedance Input Impedance External Reference Voltage
AVDD
V
AVDD <= VDD. When using an external reference voltage, decoupling capacitance should be placed from VREF to AVSS.
IREF
Current draw into VREF pin when driving with external source.
25.0
40.0
A
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ADC Magnitude Transfer Function (Linear Scale) 1 0.9 0.8 -3 dB Frequency Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
-6 dB
0
5
10
15 Frequency (kHz)
20
25
30
Figure 49. Analog-to-Digital Converter Frequency Response
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AC Characteristics
The section provides information on the AC characteristics and timing. All AC timing information assumes a standard load of 50pF on all outputs. Table 112 lists the 64K Series AC characteristics and timing.
Table 112. AC Characteristics VDD = 3.0 - 3.6V TA = -400C to 1250C Symbol Fsysclk Parameter System Clock Frequency Minimum Maximum - 0.032768 FXTAL Crystal Oscillator Frequency 0.032768 20.0 20.0 20.0 Units MHz MHz MHz Conditions Read-only from Flash memory. Program or erasure of the Flash memory. System clock frequencies below the crystal oscillator minimum require an external clock driver. TCLK = 1/Fsysclk
TXIN TXINH TXINL TXINR
Crystal Oscillator Clock Period System Clock High Time System Clock Low Time System Clock Rise Time
50 20 20 -
-
ns ns ns
3
ns
TCLK = 50ns. Slower rise times can be tolerated with longer clock periods. TCLK = 50ns. Slower fall times can be tolerated with longer clock periods.
TXINF
System Clock Fall Time
-
3
ns
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General Purpose I/O Port Input Data Sample Timing
Figure 50 illustrates timing of the GPIO Port input sampling. Table 113 lists the GPIO port input timing.
TCLK System Clock
Port Value Changes to 0 GPIO Pin Input Value
GPIO Input Data Latch
0 Latched Into Port Input Data Register GPIO Data Register Value 0 Read by eZ8 CPU
GPIO Data Read on Data Bus
Figure 50. Port Input Sample Timing Table 113. GPIO Port Input Timing Delay (ns) Parameter TS_PORT TH_PORT TSMR Abbreviation Port Input Transition to XIN Fall Setup Time (Not pictured) XIN Fall to Port Input Transition Hold Time (Not pictured) GPIO Port Pin Pulse Width to Insure STOP Mode Recovery (for GPIO Port Pins enabled as SMR sources) Min 5 6 1s Max - -
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General Purpose I/O Port Output Timing
Figure 51 and Table 114 provide timing information for GPIO Port pins.
TCLK
XIN T1 Port Output T2
Figure 51. GPIO Port Output Timing Table 114. GPIO Port Output Timing Delay (ns) Parameter Abbreviation Min Max
GPIO Port pins T1 T2 XIN Rise to Port Output Valid Delay XIN Rise to Port Output Hold Time - 2 20 -
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On-Chip Debugger Timing
Figure 52 and Table 115 provide timing information for the DBG pin. The DBG pin timing specifications assume a 4s maximum rise and fall time.
TCLK
XIN T1 DBG (Output) T2
Output Data
T3 DBG (Input)
T4
Input Data
Figure 52. On-Chip Debugger Timing Table 115. On-Chip Debugger Timing Delay (ns) Parameter DBG T1 T2 T3 T4 XIN Rise to DBG Valid Delay XIN Rise to DBG Output Hold Time DBG to XIN Rise Input Setup Time DBG to XIN Rise Input Hold Time DBG frequency - 2 10 5 30 - - - System Clock / 4 Abbreviation Min Max
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SPI Master Mode Timing
Figure 53 and Table 116 provide timing information for SPI Master mode pins. Timing is shown with SCK rising edge used to source MOSI output data, SCK falling edge used to sample MISO input data. Timing on the SS output pin(s) is controlled by software.
SCK T1 MOSI (Output) T2
Output Data
T3
MISO (Input)
Input Data
Figure 53. SPI Master Mode Timing Table 116. SPI Master Mode Timing Delay (ns) Parameter SPI Master T1 T2 T3 SCK Rise to MOSI output Valid Delay MISO input to SCK (receive edge) Setup Time MISO input to SCK (receive edge) Hold Time -5 20 0 +5 Abbreviation Min Max
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SPI Slave Mode Timing
Figure 54 and Table 117 provide timing information for the SPI slave mode pins. Timing is shown with SCK rising edge used to source MISO output data, SCK falling edge used to sample MOSI input data.
SCK T1 MISO (Output) T2
Output Data
T3
MOSI (Input) T4 SS (Input)
Input Data
Figure 54. SPI Slave Mode Timing Table 117. SPI Slave Mode Timing Delay (ns) Parameter SPI Slave T1 SCK (transmit edge) to MISO output Valid Delay 2 * Xin period 0 3 * Xin period 1 * Xin period 3 * Xin period + 20 nsec Abbreviation Min Max
T2 T3 T4
MOSI input to SCK (receive edge) Setup Time MOSI input to SCK (receive edge) Hold Time SS input assertion to SCK setup
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I2C Timing
Figure 55 and Table 118 provide timing information for I2C pins.
SCL (Output) T1 SDA (Output) T2 Input Data T3
Output Data
SDA (Input)
Figure 55. I2C Timing Table 118. I2C Timing Delay (ns) Parameter IC T1 T2 T3 SCL Fall to SDA output delay SDA Input to SCL rising edge Setup Time SDA Input to SCL falling edge Hold Time 0 0 SCL period/4
2
Abbreviation
Minimum
Maximum
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UART Timing
Figure 56 and Table 119 provide timing information for UART pins for the case where the Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that the Driver Enable polarity has been configured to be Active Low and is represented here by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data register has been loaded with data prior to CTS assertion.
CTS (Input)
T1 DE (Output) T2 TXD (Output) T3
Start
Bit 0
Bit 1
Bit 7
Parity
Stop
End of Stop Bit(s)
Figure 56. UART Timing with CTS Table 119. UART Timing with CTS Delay (ns) Parameter Abbreviation T1 T2 T3 CTS Fall to DE Assertion Delay Minimum Maximum
2 * XIN period 2 * XIN period + 1 Bit period 1 Bit period + 1 * XIN period
DE Assertion to TXD Falling Edge (Start) Delay 1 Bit period End of Stop Bit(s) to DE Deassertion Delay
1 * XIN period 2 * XIN period
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Figure 57 and Table 120 provide timing information for UART pins for the case where the Clear To Send input signal (CTS) is not used for flow control. In this example, it is assumed that the Driver Enable polarity has been configured to be Active Low and is represented here by DE. DE asserts after the UART Transmit Data Register has been written. DE remains asserted for multiple characters as long as the Transmit Data register is written with the next character before the current character has completed.
DE (Output) T1 TXD (Output) T2
Start
Bit 0
Bit 1
Bit 7
Parity
Stop
End of Stop Bit(s)
Figure 57. UART Timing without CTS Table 120. UART Timing without CTS Delay (ns) Parameter Abbreviation T1 T2 DE Assertion to TXD Falling Edge (Start) Delay End of Stop Bit(s) to DE Deassertion Delay Minimum 1 Bit period 1 * XIN period Maximum 1 Bit period + 1 * XIN period 2 * XIN period
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eZ8 CPU Instruction Set
Assembly Language Programming Introduction
The eZ8 CPU assembly language provides a means for writing an application program without having to be concerned with actual memory addresses or machine instruction formats. A program written in assembly language is called a source program. Assembly language allows the use of symbolic addresses to identify memory locations. It also allows mnemonic codes (opcodes and operands) to represent the instructions themselves. The opcodes identify the instruction while the operands represent memory locations, registers, or immediate data values. Each assembly language program consists of a series of symbolic commands called statements. Each statement can contain labels, operations, operands and comments. Labels can be assigned to a particular instruction step in a source program. The label identifies that step in the program as an entry point for use by other instructions. The assembly language also includes assembler directives that supplement the machine instruction. The assembler directives, or pseudo-ops, are not translated into a machine instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the assembly process. The source program is processed (assembled) by the assembler to obtain a machine language program called the object code. The object code is executed by the eZ8 CPU. An example segment of an assembly language program is detailed in the following example. Assembly Language Source Program Example
JP START START:
; Everything after the semicolon is a comment. ; A label called "START". The first instruction (JP START) in this ; example causes program execution to jump to the point within the ; program where the START label occurs. ; A Load (LD) instruction with two operands. The first operand, ; Working Register R4, is the destination. The second operand, ; Working Register R7, is the source. The contents of R7 is ; written into R4. ; Another Load (LD) instruction with two operands. ; The first operand, Extended Mode Register Address 234H, ; identifies the destination. The second operand, Immediate Data
LD R4, R7
LD 234H, #%01
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; value 01H, is the source. The value 01H is written into the ; Register at address 234H.
Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as `destination, source'. After assembly, the object code usually has the operands in the order 'source, destination', but ordering is opcode-dependent. The following instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler. This binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. Example 1: If the contents of Registers 43H and 08H are added and the result is stored in 43H, the assembly syntax and resulting object code is: Assembly Language Syntax Example 1
Assembly Language Code ADD Object Code 04 43H, 08 08H 43 (ADD dst, src) (OPC src, dst)
Example 2: In general, when an instruction format requires an 8-bit register address, that address can specify any register location in the range 0 - 255 or, using Escaped Mode Addressing, a Working Register R0 - R15. If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H, the assembly syntax and resulting object code is: Assembly Language Syntax Example 2
Assembly Language Code ADD Object Code 04 43H, E8 R8 43 (ADD dst, src) (OPC src, dst)
See the device-specific Product Specification to determine the exact register file range available. The register file size varies, depending on the device type.
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition codes, status flags, and address modes are represented by a notational shorthand that is described in Table 121.
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.
Table 121. Notational Shorthand Notation Description b cc DA ER IM Ir IR Irr IRR p r R RA Bit Condition Code Direct Address Extended Addressing Register Immediate Data Indirect Working Register Indirect Register Indirect Working Register Pair Indirect Register Pair Polarity Working Register Register Relative Address Operand Range b -- Addrs Reg #Data @Rn @Reg @RRp @Reg p Rn Reg X b represents a value from 0 to 7 (000B to 111B). See Condition Codes overview in the eZ8 CPU User Manual. Addrs. represents a number in the range of 0000H to FFFFH Reg. represents a number in the range of 000H to FFFH Data is a number between 00H to FFH n = 0 -15 Reg. represents a number in the range of 00H to FFH p = 0, 2, 4, 6, 8, 10, 12, or 14 Reg. represents an even number in the range 00H to FEH Polarity is a single bit binary value of either 0B or 1B. n = 0 - 15 Reg. represents a number in the range of 00H to FFH X represents an index in the range of +127 to -128 which is an offset relative to the address of the next instruction p = 0, 2, 4, 6, 8, 10, 12, or 14 Reg. represents an even number in the range of 00H to FEH Vector represents a number in the range of 00H to FFH The register or register pair to be indexed is offset by the signed Index value (#Index) in a +127 to -128 range.
rr RR Vector X
Working Register Pair Register Pair Vector Address Indexed
RRp Reg Vector #Index
Table 122 contains additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections.
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Table 122. Additional Symbols Symbol dst src @ SP PC FLAGS RP # B % H Definition Destination Operand Source Operand Indirect Address Prefix Stack Pointer Program Counter Flags Register Register Pointer Immediate Operand Prefix Binary Number Suffix Hexadecimal Number Prefix Hexadecimal Number Suffix
Assignment of a value is indicated by an arrow. For example, dst dst + src indicates the source data is added to the destination data and the result is stored in the destination location.
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Condition Codes
The C, Z, S and V flags control the operation of the conditional jump (JP cc and JR cc) instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc), which forms Bits 7:4 of the conditional jump instructions. The condition codes are summarized in Table 123. Some binary condition codes can be created using more than one assembly code mnemonic. The result of the flag test operation decides if the conditional jump is executed.
Table 123. Condition Codes Assembly Mnemonic Definition F LT LE ULE OV Ml Z EQ C ULT Always False Less Than Less Than or Equal Unsigned Less Than or Equal Overflow Minus Zero Equal Carry Unsigned Less Than
Binary 0000 0001 0010 0011 0100 0101 0110 0110 0111 0111 1000 1001 1010 1011 1100 1101 1110 1110 1111 1111
Hex 0 1 2 3 4 5 6 6 7 7 8 9 A B C D E E F F
Flag Test Operation - (S XOR V) = 1 (Z OR (S XOR V)) = 1 (C OR Z) = 1 V=1 S=1 Z=1 Z=1 C=1 C=1 - (S XOR V) = 0 (Z OR (S XOR V)) = 0 (C = 0 AND Z = 0) = 1 V=0 S=0 Z=0 Z=0 C=0
T (or blank) Always True GE GT UGT NOV PL NZ NE NC UGE Greater Than or Equal Greater Than Unsigned Greater Than No Overflow Plus Non-Zero Not Equal No Carry
Unsigned Greater Than or Equal C = 0
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eZ8 CPU Instruction Classes
eZ8 CPU instructions can be divided functionally into the following groups:
* * * * * * * *
Arithmetic Bit Manipulation Block Transfer CPU Control Load Logical Program Control Rotate and Shift
Tables 124 through 131 contain the instructions belonging to each group and the number of operands required for each instruction. Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category. Within these tables, the source operand is identified as 'src', the destination operand is 'dst' and a condition code is 'cc'.
Table 124. Arithmetic Instructions Mnemonic ADC ADCX ADD ADDX CP CPC CPCX CPX DA DEC DECW INC INCW MULT Operands dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst, src dst dst dst dst dst dst Instruction Add with Carry Add with Carry using Extended Addressing Add Add using Extended Addressing Compare Compare with Carry Compare with Carry using Extended Addressing Compare using Extended Addressing Decimal Adjust Decrement Decrement Word Increment Increment Word Multiply
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Table 124. Arithmetic Instructions (Continued) Mnemonic SBC SBCX SUB SUBX Operands dst, src dst, src dst, src dst, src Instruction Subtract with Carry Subtract with Carry using Extended Addressing Subtract Subtract using Extended Addressing
Table 125. Bit Manipulation Instructions Mnemonic BCLR BIT BSET BSWAP CCF RCF SCF TCM TCMX TM TMX Operands bit, dst p, bit, dst bit, dst dst -- -- -- dst, src dst, src dst, src dst, src Instruction Bit Clear Bit Set or Clear Bit Set Bit Swap Complement Carry Flag Reset Carry Flag Set Carry Flag Test Complement Under Mask Test Complement Under Mask using Extended Addressing Test Under Mask Test Under Mask using Extended Addressing
Table 126. Block Transfer Instructions Mnemonic LDCI LDEI Operands dst, src dst, src Instruction Load Constant to/from Program Memory and Auto-Increment Addresses Load External Data to/from Data Memory and Auto-Increment Addresses
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Table 127. CPU Control Instructions Mnemonic ATM CCF DI EI HALT NOP RCF SCF SRP STOP WDT Operands -- -- -- -- -- -- -- -- src -- -- Instruction Atomic Execution Complement Carry Flag Disable Interrupts Enable Interrupts HALT Mode No Operation Reset Carry Flag Set Carry Flag Set Register Pointer STOP Mode Watch-Dog Timer Refresh
Table 128. Load Instructions Mnemonic CLR LD LDC LDCI LDE LDEI LDWX LDX LEA POP POPX PUSH PUSHX Operands Instruction dst dst, src dst, src dst, src dst, src dst, src dst, src dst, src Clear Load Load Constant to/from Program Memory Load Constant to/from Program Memory and Auto-Increment Addresses Load External Data to/from Data Memory Load External Data to/from Data Memory and Auto-Increment Addresses Load Word using Extended Addressing Load using Extended Addressing
dst, X(src) Load Effective Address dst dst src src Pop Pop using Extended Addressing Push Push using Extended Addressing
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Table 129. Logical Instructions Mnemonic Operands Instruction AND ANDX COM OR ORX XOR XORX dst, src dst, src dst dst, src dst, src dst, src dst, src Logical AND Logical AND using Extended Addressing Complement Logical OR Logical OR using Extended Addressing Logical Exclusive OR Logical Exclusive OR using Extended Addressing
Table 130. Program Control Instructions Mnemonic BRK BTJ BTJNZ BTJZ CALL DJNZ IRET JP JP cc JR JR cc RET TRAP Operands -- Instruction On-Chip Debugger Break
p, bit, src, DA Bit Test and Jump bit, src, DA bit, src, DA dst dst, src, RA -- dst dst DA DA -- vector Bit Test and Jump if Non-Zero Bit Test and Jump if Zero Call Procedure Decrement and Jump Non-Zero Interrupt Return Jump Jump Conditional Jump Relative Jump Relative Conditional Return Software Trap
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Table 131. Rotate and Shift Instructions Mnemonic BSWAP RL RLC RR RRC SRA SRL SWAP Operands dst dst dst dst dst dst dst dst Instruction Bit Swap Rotate Left Rotate Left through Carry Rotate Right Rotate Right through Carry Shift Right Arithmetic Shift Right Logical Swap Nibbles
eZ8 CPU Instruction Summary
Table 132 summarizes the eZ8 CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch, and the number of CPU clock cycles required for the instruction execution.
.
Table 132. eZ8 CPU Instruction Summary Assembly Mnemonic ADC dst, src Address Mode Symbolic Operation dst dst + src + C dst r r R R R IR ADCX dst, src dst dst + src + C ER ER Flags Notation: src r Ir R IR IM IM ER IM Opcode(s) (Hex) C 12 13 14 15 16 17 18 19 0 = Reset to 0 1 = Set to 1 * * * * 0 * * Flags Z * S * Fetch Instr. V D H Cycles Cycles * 0 * 2 2 3 3 3 3 4 4 3 4 3 4 3 4 3 3
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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Table 132. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic ADD dst, src Address Mode Symbolic Operation dst dst + src dst r r R R R IR ADDX dst, src dst dst + src dst dst AND src ER ER AND dst, src r r R R R IR ANDX dst, src dst dst AND src ER ER ATM Block all interrupt and DMA requests during execution of the next 3 instructions dst[bit] 0 dst[bit] p Debugger Break dst[bit] 1 dst[7:0] dst[0:7] r R r Ir r r src r Ir R IR IM IM ER IM r Ir R IR IM IM ER IM Opcode(s) (Hex) C 02 03 04 05 06 07 08 09 52 53 54 55 56 57 58 59 2F * * 0 * * 0 * * * * 0 * * Flags Z * S * Fetch Instr. V D H Cycles Cycles * 0 * 2 2 3 3 3 3 4 4 2 2 3 3 3 3 4 4 1 3 4 3 4 3 4 3 3 3 4 3 4 3 4 3 3 2
BCLR bit, dst BIT p, bit, dst BRK BSET bit, dst BSWAP dst
E2 E2 00 E2 D5 F6 F7
X -
* * * * -
* * * * -
0 0 0 0 -
-
-
2 2 1 2 2 3 3
2 2 1 2 2 3 4
BTJ p, bit, src, dst if src[bit] = p PC PC + X Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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244
Table 132. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Address Mode Symbolic Operation dst src r Ir r Ir IRR DA Opcode(s) (Hex) C F6 F7 F6 F7 D4 D6 EF R IR COM dst dst ~dst R IR CP dst, src dst - src r r R R R IR CPC dst, src dst - src - C r r R R R IR CPCX dst, src dst - src - C ER ER Flags Notation: r Ir R IR IM IM r Ir R IR IM IM ER IM B0 B1 60 61 A2 A3 A4 A5 A6 A7 1F A2 1F A3 1F A4 1F A5 1F A6 1F A7 1F A8 1F A9 0 = Reset to 0 1 = Set to 1 * * * * * * * * * * * * * * 0 * Flags Z S Fetch Instr. V D H Cycles Cycles 3 3 3 3 2 3 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 5 5 3 4 3 4 6 3 2 2 3 2 3 3 4 3 4 3 4 3 4 3 4 3 4 3 3
BTJNZ bit, src, dst if src[bit] = 1 PC PC + X BTJZ bit, src, dst if src[bit] = 0 PC PC + X SP SP -2 @SP PC PC dst C ~C dst 00H
CALL dst
CCF CLR dst
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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245
Table 132. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic CPX dst, src Address Mode Symbolic Operation dst - src dst DA(dst) dst dst - 1 dst dst - 1 IRQCTL[7] 0 dst dst - 1 if dst 0 PC PC + X IRQCTL[7] 1 HALT Mode dst dst + 1 R IR r INCW dst dst dst + 1 FLAGS @SP SP SP + 1 PC @SP SP SP + 2 IRQCTL[7] 1 PC dst DA IRR JP cc, dst Flags Notation: if cc is true PC dst DA RR IRR IRET r dst ER ER DA dst R IR DEC dst R IR DECW dst RR IRR DI DJNZ dst, RA src ER IM Opcode(s) (Hex) C A8 A9 40 41 30 31 80 81 8F 0A-FA * * * * * * * * * X * Flags Z * S * Fetch Instr. V D H Cycles Cycles * 4 4 2 2 2 2 2 2 1 2 3 3 2 3 2 3 5 6 2 3
EI HALT INC dst
9F 7F 20 21 0E-FE A0 A1 BF
-
*
*
*
-
-
1 1 2 2 1
2 2 2 3 2 5 6 5
-
*
*
*
-
-
2 2
*
*
*
*
*
*
1
JP dst
8D C4 0D-FD
-
-
-
-
-
-
3 2
2 3 2
-
-
-
-
-
-
3
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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246
Table 132. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic JR dst JR cc, dst LD dst, rc Address Mode Symbolic Operation PC PC + X if cc is true PC PC + X dst src dst DA DA r r X(r) r R R R IR Ir IR LDC dst, src dst src r Ir Irr LDCI dst, src dst src rr+1 rr rr + 1 dst src dst src rr+1 rr rr + 1 dst src Ir Irr r Irr LDEI dst, src Ir Irr ER IM X(r) r Ir R IR IM IM r R Irr Irr r Irr Ir Irr r Irr Ir ER src Opcode(s) (Hex) C 8B 0B-FB 0C-FC C7 D7 E3 E4 E5 E6 E7 F3 F5 C2 C5 D2 C3 D3 82 92 83 93 1F E8 Flags Z S Fetch Instr. V D H Cycles Cycles 2 2 2 3 3 2 3 3 3 3 2 3 2 2 2 2 2 2 2 2 2 5 2 2 2 3 4 3 2 4 2 3 3 3 5 9 5 9 9 5 5 9 9 4
LDE dst, src
LDWX dst, src Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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247
Table 132. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic LDX dst, src Address Mode Symbolic Operation dst src dst r Ir R IR r X(rr) ER ER IRR IRR ER ER LEA dst, X(src) dst src + X dst[15:0] dst[15:8] * dst[7:0] No operation dst dst OR src r r R R R IR ORX dst, src dst dst OR src ER ER Flags Notation: r Ir R IR IM IM ER IM r rr MULT dst NOP OR dst, src RR src ER ER IRR IRR X(rr) r r Ir R IR ER IM X(r) X(rr) Opcode(s) (Hex) C 84 85 86 87 88 89 94 95 96 97 E8 E9 98 99 F4 0F 42 43 44 45 46 47 48 49 0 = Reset to 0 1 = Set to 1 * * 0 * * 0 Flags Z S Fetch Instr. V D H Cycles Cycles 3 3 3 3 3 3 3 3 3 3 4 4 3 3 2 1 2 2 3 3 3 3 4 4 2 3 4 5 4 4 2 3 4 5 2 2 3 5 8 2 3 4 3 4 3 4 3 3
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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248
Table 132. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic POP dst Address Mode Symbolic Operation dst @SP SP SP + 1 dst @SP SP SP + 1 SP SP - 1 @SP src dst R IR ER R IR IM PUSHX src RCF RET RL dst
C D7 D6 D5 D4 D3 D2 D1 D0 dst
src
Opcode(s) (Hex) C 50 51 D8 70 71 1F 70 C8 CF AF 0 * -
Flags Z S -
Fetch Instr. V D H Cycles Cycles 2 2 2 3 2 2 3 2 2 2 4 2 3
POPX dst PUSH src
-
-
-
-
-
3 2 2 3
SP SP - 1 @SP src C0 PC @SP SP SP + 2
ER
*
*
*
-
-
3 1 1 2 2
R IR
90 91
RLC dst
C D7 D6 D5 D4 D3 D2 D1 D0 dst
R IR R
D7 D6 D5 D4 D3 D2 D1 D0 dst C
10 11 E0 E1
*
*
*
*
-
-
2 2
2 3 2 3
RR dst
*
*
*
*
-
-
2 2
IR
RRC dst
D7 D6 D5 D4 D3 D2 D1 D0 dst C
R IR
C0 C1
*
*
*
*
-
-
2 2
2 3
Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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249
Table 132. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic SBC dst, src Address Mode Symbolic Operation dst dst - src - C dst r r R R R IR SBCX dst, src dst dst - src - C C1 R
D7 D6 D5 D4 D3 D2 D1 D0 dst C
src r Ir R IR IM IM ER IM
Opcode(s) (Hex) C 32 33 34 35 36 37 38 39 DF D0 D1 1 * * *
Flags Z * S *
Fetch Instr. V D H Cycles Cycles * 1 * 2 2 3 3 3 3 3 4 3 4 3 4 3 3 2 2 3
ER ER
*
*
*
1
*
4 4
SCF SRA dst
*
*
0
-
-
1 2 2
IR
SRL dst
0
D7 D6 D5 D4 D3 D2 D1 D0 dst
C
R IR
1F C0 1F C1 IM 01 6F
*
*
0
*
-
-
3 3
2 3 2 2 3 4 3 4 3 4 3 3 2 3
SRP src STOP SUB dst, src
RP src STOP Mode dst dst - src r r R R R IR dst dst - src dst[7:4] dst[3:0]
*
*
*
*
1
*
2 1 2 2 3 3 3 3
r Ir R IR IM IM ER IM
22 23 24 25 26 27 28 29 F0 F1
SUBX dst, src
ER ER
*
*
*
*
1
*
4 4
SWAP dst
R IR
X
*
*
X
-
-
2 2
Flags Notation:
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
0 = Reset to 0 1 = Set to 1
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Table 132. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic TCM dst, src Address Mode Symbolic Operation (NOT dst) AND src dst r r R R R IR TCMX dst, src (NOT dst) AND src ER ER TM dst, src dst AND src r r R R R IR TMX dst, src dst AND src SP SP - 2 @SP PC SP SP - 1 @SP FLAGS PC @Vector ER ER TRAP Vector src r Ir R IR IM IM ER IM r Ir R IR IM IM ER IM Vector Opcode(s) (Hex) C 62 63 64 65 66 67 68 69 72 73 74 75 76 77 78 79 F2 * * 0 * * 0 * * 0 Flags Z * S * Fetch Instr. V D H Cycles Cycles 0 2 2 3 3 3 3 4 4 2 2 3 3 3 3 4 4 2 3 4 3 4 3 4 3 3 3 4 3 4 3 4 3 3 6
WDT Flags Notation:
5F * = Value is a function of the result of the operation. - = Unaffected X = Undefined
-
-
-
-
-
-
1
2
0 = Reset to 0 1 = Set to 1
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251
Table 132. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic XOR dst, src Address Mode Symbolic Operation dst dst XOR src dst r r R R R IR XORX dst, src dst dst XOR src ER ER Flags Notation: src r Ir R IR IM IM ER IM Opcode(s) (Hex) C B2 B3 B4 B5 B6 B7 B8 B9 0 = Reset to 0 1 = Set to 1 * * 0 Flags Z * S * Fetch Instr. V D H Cycles Cycles 0 2 2 3 3 3 3 4 4 3 4 3 4 3 4 3 3
* = Value is a function of the result of the operation. - = Unaffected X = Undefined
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252
Flags Register
The Flags Register contains the status information regarding the most recent arithmetic, logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z and S) can be tested for use with conditional jump instructions. Two flags (H and D) cannot be tested and are used for Binary-Coded Decimal (BCD) arithmetic. The two remaining bits, User Flags (F1 and F2), are available as general-purpose status bits. User Flags are unaffected by arithmetic operations and must be set or cleared by instructions. The User Flags cannot be used with conditional Jumps. They are undefined at initial power-up and are unaffected by Reset. Figure 58 illustrates the flags and their bit positions in the Flags Register.
Bit 7 C Z S V D Bit 0 H F2 F1 Flags Register User Flags Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag U = Undefined Figure 58. Flags Register
Interrupts, the Software Trap (TRAP) instruction, and Illegal Instruction Traps all write the value of the Flags Register to the stack. Executing an Interrupt Return (IRET) instruction restores the value saved on the stack into the Flags Register.
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253
Opcode Maps
A description of the opcode map data and the abbreviations are provided in Figure 59 and Table 132. Figures 60 and 61 provide information on each of the eZ8 CPU instructions.
Opcode Lower Nibble Fetch Cycles Instruction Cycles
4
3.3 Opcode Upper Nibble
A
CP R2,R1
First Operand After Assembly
Second Operand After Assembly
Figure 59. Opcode Map Cell Description
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254
Table 132. Opcode Map Abbreviations Abbreviation b cc X DA ER IM Ir IR Irr Description Bit position Condition code Abbreviation IRR p Description Indirect Register Pair Polarity (0 or 1) 4-bit Working Register 8-bit register
8-bit signed index or displacement r Destination address Extended Addressing register Immediate data value Indirect Working Register Indirect register Indirect Working Register Pair R
r1, R1, Ir1, Irr1, IR1, rr1, Destination address RR1, IRR1, ER1 r2, R2, Ir2, Irr2, IR2, rr2, Source address RR2, IRR2, ER2 RA rr RR Relative Working Register Pair Register Pair
PS019915-1005
Opcode Maps
Z8 Encore!(R) 64K Series Product Specification
255
0
1.2
1
2.2
2
2.3
3
2.4
4
3.3
5
3.4
6
3.3
Lower Nibble (Hex) 7 8 9
3.4 4.3 4.3
A
2.3 r1,X
B
2.2
C
2.2
D
3.2
E
1.2
F
1.2
0
BRK
2.2
SRP
IM 2.3
ADD
r1,r2 2.3
ADD
r1,Ir2 2.4
ADD
R2,R1 3.3
ADD
IR2,R1 3.4
ADD
R1,IM 3.3
ADD
3.4
ADDX ADDX DJNZ
4.3 4.3
JR
cc,X
LD
r1,IM
JP
cc,DA
INC
r1
NOP
See 2nd Opcode Map 1,2
IR1,IM ER2,ER1 IM,ER1
1
RLC
R1 2.2
RLC
IR1 2.3
ADC
r1,r2 2.3
ADC
r1,Ir2 2.4
ADC
R2,R1 3.3
ADC
IR2,R1 3.4
ADC
R1,IM 3.3
ADC
3.4
ADCX ADCX
4.3 4.3
IR1,IM ER2,ER1 IM,ER1
2
INC
R1 2.2
INC
IR1 2.3
SUB
r1,r2 2.3
SUB
r1,Ir2 2.4
SUB
R2,R1 3.3
SUB
IR2,R1 3.4
SUB
R1,IM 3.3
SUB
3.4
SUBX SUBX
4.3 4.3
ATM
IR1,IM ER2,ER1 IM,ER1
3
DEC
R1 2.2
DEC
IR1 2.3
SBC
r1,r2 2.3
SBC
r1,Ir2 2.4
SBC
R2,R1 3.3
SBC
IR2,R1 3.4
SBC
R1,IM 3.3
SBC
3.4
SBCX SBCX
4.3 4.3
IR1,IM ER2,ER1 IM,ER1
4
DA
R1 2.2
DA
IR1 2.3
OR
r1,r2 2.3
OR
r1,Ir2 2.4
OR
R2,R1 3.3
OR
IR2,R1 3.4
OR
R1,IM 3.3
OR
3.4
ORX
4.3
ORX
4.3 1.2
IR1,IM ER2,ER1 IM,ER1
5
POP
R1 2.2
POP
IR1 2.3
AND
r1,r2 2.3
AND
r1,Ir2 2.4
AND
R2,R1 3.3
AND
IR2,R1 3.4
AND
R1,IM 3.3
AND
3.4
ANDX ANDX
4.3 4.3
WDT
1.2
IR1,IM ER2,ER1 IM,ER1
6 Upper Nibble (Hex)
COM
R1 2.2
COM
IR1 2.3 IR2 2.6 IRR1 2.3
TCM
r1,r2 2.3
TCM
r1,Ir2 2.4
TCM
R2,R1 3.3
TCM
IR2,R1 3.4
TCM
R1,IM 3.3
TCM
3.4
TCMX TCMX
4.3 4.3
STOP
1.2
IR1,IM ER2,ER1 IM,ER1
7
PUSH PUSH
R2 2.5
TM
r1,r2 2.5
TM
r1,Ir2 2.9
TM
R2,R1 3.2
TM
IR2,R1 3.3
TM
R1,IM 3.4
TM
3.5
TMX
3.4
TMX
3.4
HALT
1.2
IR1,IM ER2,ER1 IM,ER1
8
DECW DECW
RR1 2.2
LDE
r1,Irr2 2.5
LDEI
Ir1,Irr2 2.9
LDX
r1,ER2 3.2
LDX
3.3
LDX
3.4
LDX
3.5
LDX
3.3
LDX
rr1,r2,X 3.5
DI
1.2
Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X
9
RL
R1 2.5
RL
IR1 2.6 IRR1 2.3
LDE
r2,Irr1 2.3
LDEI
Ir2,Irr1 2.4
LDX
r2,ER1 3.3
LDX
3.4
LDX
3.3
LDX
3.4
LEA
4.3
LEA
rr1,rr2,X 4.3
EI
1.4
Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X
A
INCW INCW
RR1 2.2
CP
r1,r2 2.3
CP
r1,Ir2 2.4
CP
R2,R1 3.3
CP
IR2,R1 3.4
CP
R1,IM 3.3
CP
3.4
CPX
4.3
CPX
4.3
RET
1.5
IR1,IM ER2,ER1 IM,ER1
B
CLR
R1 2.2
CLR
IR1 2.3
XOR
r1,r2 2.5
XOR
r1,Ir2 2.9
XOR
R2,R1 2.3
XOR
IR2,R1 2.9
XOR
R1,IM
XOR
3.4
XORX XORX
3.2
IRET
1.2
IR1,IM ER2,ER1 IM,ER1
C
RRC
R1 2.2
RRC
IR1 2.3
LDC
r1,Irr2 2.5
LDCI
Ir1,Irr2 2.9
JP
IRR1 2.6 IRR1 3.2
LDC
Ir1,Irr2 2.2 R1 3.3 3.3 DA 3.2
LD
r1,r2,X 3.4
PUSHX
ER2 3.2
RCF
1.2
D
SRA
R1 2.2
SRA
IR1 2.3
LDC
r2,Irr1 2.2
LDCI
Ir2,Irr1 2.3
CALL BSWAP CALL
LD
r2,r1,X 3.3
POPX
ER1 4.2 4.2
SCF
1.2
E
RR
R1 2.2
RR
IR1 2.3 IR1
BIT
p,b,r1 2.6 Vector
LD
r1,Ir2 2.3
LD
R2,R1 2.8
LD
IR2,R1 3.3
LD
R1,IM 3.3
LD
3.4
LDX
LDX
CCF
IR1,IM ER2,ER1 IM,ER1
F
SWAP SWAP TRAP
R1
LD
Ir1,r2
MULT
RR1
LD
R2,IR1
BTJ
BTJ
p,b,r1,X p,b,Ir1,X
Figure 60. First Opcode Map
PS019915-1005
Opcode Maps
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256
0 0
1
2
3
4
5
6
Lower Nibble (Hex) 7 8 9
A
B
C
D
E
F
1
2
3
4
5
6 Upper Nibble (Hex)
3,2
7
PUSH
IM
8
9
3.3 3.4 4.3 4.4 4.3 4.4 5.3 5.3
A
CPC
r1,r2
CPC
r1,Ir2
CPC
R2,R1
CPC
IR2,R1
CPC
R1,IM
CPC
CPCX CPCX
IR1,IM ER2,ER1 IM,ER1
B
3.2 3.3
C
SRL
R1
SRL
IR1
D
5,4
E
LDWX
ER2,ER1
F
Figure 61. Second Opcode Map after 1FH
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257
Packaging
Figure 62 illustrates the 40-pin PDIP (plastic dual-inline package) available for the Z8X1601, Z8X2401, Z8X3201, Z8X4801, and Z8X6401 devices.
Figure 62. 40-Lead Plastic Dual-Inline Package (PDIP)
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Packaging
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258
Figure 63 illustrates the 44-pin LQFP (low profile quad flat package) available for the Z8X1621, Z8X2421, Z8X3221, Z8X4821, and Z8X6421 devices.
A A2 A1
HD D
E
HE
DETAIL A
LE c e b
L
0-7
Figure 63. 44-Lead Low-Profile Quad Flat Package (LQFP)
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Packaging
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259
Figure 64 illustrates the 44-pin PLCC (plastic lead chip carrier) package available for the Z8X1621, Z8X2421, Z8X3221, Z8X4821, and Z8X6421 devices.
A D D1 45 7 6 1 40 39 1.321/1.067 0.052/0.042
e
A1 D2 DIM. FROM CENTER TO CENTER OF RADII 0.71/0.51 .028/.020
SYMBOL A A1 D/E D1/E1 D2 e
MILLIMETER MIN 4.27 2.41 17.40 16.51 15.24 MAX 4.57 2.92 17.65 16.66 16.00 MIN
INCH MAX 0.180 0.115 0.695 0.656 0.630
0.168 0.095 0.685 0.650 0.600
E1 E
M
0.51/0.36 0.020/0.014
0.81/0.66 0.032/0.026 17 18 28 29 R 1.14/0.64 0.045/0.025
1.27 BSC
0.050 BSC
NOTES: 1. CONTROLLING DIMENSION : INCH 2. LEADS ARE COPLANAR WITHIN 0.004". 3. DIMENSION : MM INCH
Figure 64. 44-Lead Plastic Lead Chip Carrier Package (PLCC)
Figure 64 illustrates the 64-pin LQFP (low-profile quad flat package) available for the Z8X1622, Z8X2422, Z8X3222, Z8X4822, and Z8X6422 devices.
HD D
A A2 A1
E
HE
DETAIL A
LE c e b
L
0-7
Figure 65. 64-Lead Low-Profile Quad Flat Package (LQFP)
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Packaging
Z8 Encore!(R) 64K Series Product Specification
260
Figure 66 illustrates the 68-pin PLCC (plastic lead chip carrier) package available for the Z8X1622, Z8X2422, Z8X3222, Z8X4822, and Z8X6422 devices.
Figure 66. 68-Lead Plastic Lead Chip Carrier Package (PLCC)
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Packaging
Z8 Encore!(R) 64K Series Product Specification
261
Figure 67 illustrates the 80-pin QFP (quad flat package) available for the Z8X4823 and Z8X6423 devices.
HD D A2
64
41
A1
SYMBOL A1 A2 b c
MILLIMETER MIN MAX 0.38 2.80 0.45 0.20 24.15 20.10 18.15 14.10 MIN .004 .102 .012 .005 .933 .783 .697 .547
INCH MAX .015 .110 .018 .008 .951 .791 .715 .555
65
40
0.10 2.60 0.30 0.13 23.70 19.90 17.70 13.90
E
HE
HD D HE
80
25
E e L
c
0.80 BSC 0.70 1.10
.0315 BSC .028 .043
1
b e
24 DETAIL A
NOTES: CONTROLLING DIMENSIONS : MILLIMETER 2. LEAD COPLANARITY : MAX .10 .004"
L
0-10
DETAIL A
Figure 67. 80-Lead Quad-Flat Package (QFP)
PS019915-1005
Packaging
Z8 Encore!(R) 64K Series Product Specification
262
Ordering Information
16-Bit Timers w/PWM 10-Bit A/D Channels UARTs with IrDA
Part Number
Interrupts
I/O Lines
Flash
RAM
Z8F642x with 64KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0 to 70C Z8F6421PM020SC Z8F6421AN020SC Z8F6421VN020SC Z8F6422AR020SC Z8F6422VS020SC Z8F6423FT020SC 64KB 64KB 64KB 64KB 64KB 64KB 4KB 4KB 4KB 4KB 4KB 4KB 29 23 31 23 31 23 46 24 46 24 60 24 3 3 3 4 4 4 8 8 8 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package 2 QFP 80-pin package
Extended Temperature: -40 to +105C Z8F6421PM020EC Z8F6421AN020EC Z8F6421VN020EC Z8F6422AR020EC Z8F6422VS020EC Z8F6423FT020EC 64KB 64KB 64KB 64KB 64KB 64KB 4KB 4KB 4KB 4KB 4KB 4KB 29 23 31 23 31 23 46 24 46 24 60 24 3 3 3 4 4 4 8 8 8 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package 2 QFP 80-pin package
Automotive/Industrial Temperature: -40 to +125C Z8F6421PM020AC Z8F6421AN020AC Z8F6421VN020AC Z8F6422AR020AC Z8F6422VS020AC Z8F6423FT020AC 64KB 64KB 64KB 64KB 64KB 64KB 4KB 4KB 4KB 4KB 4KB 4KB 29 23 31 23 31 23 46 24 46 24 60 24 3 3 3 4 4 4 8 8 8 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package 2 QFP 80-pin package
Note: Replace C with G for lead-free packaging.
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Description Ordering Information
SPI
Z8 Encore!(R) 64K Series Product Specification
263
16-Bit Timers w/PWM
10-Bit A/D Channels
Part Number
UARTs with IrDA
Interrupts
I/O Lines
Flash
RAM
Z8F482x with 48KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0 to 70C Z8F4821PM020SC Z8F4821AN020SC Z8F4821VN020SC Z8F4822AR020SC Z8F4822VS020SC Z8F4823FT020SC 48KB 48KB 48KB 48KB 48KB 48KB 4KB 4KB 4KB 4KB 4KB 4KB 29 23 31 23 31 23 46 24 46 24 60 24 3 3 3 4 4 4 8 8 8 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package 2 QFP 80-pin package
Extended Temperature: -40 to +105C Z8F4821PM020EC Z8F4821AN020EC Z8F4821VN020EC Z8F4822AR020EC Z8F4822VS020EC Z8F4823FT020EC 48KB 48KB 48KB 48KB 48KB 48KB 4KB 4KB 4KB 4KB 4KB 4KB 29 23 31 23 31 23 46 24 46 24 46 24 3 3 3 4 4 4 8 8 8 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package 2 QFP 80-pin package
Automotive/Industrial Temperature: -40 to +125C Z8F4821PM020AC Z8F4821AN020AC Z8F4821VN020AC Z8F4822AR020AC Z8F4822VS020AC Z8F4823FT020AC 48KB 48KB 48KB 48KB 48KB 48KB 4KB 4KB 4KB 4KB 4KB 4KB 29 23 31 23 31 23 46 24 46 24 46 24 3 3 3 4 4 4 8 8 8 12 12 12 1 1 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package 2 QFP 80-pin package
Note: Replace C with G for lead-free packaging.
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Description Ordering Information
SPI
Z8 Encore!(R) 64K Series Product Specification
264
16-Bit Timers w/PWM
10-Bit A/D Channels
Part Number
UARTs with IrDA
Interrupts
I/O Lines
Flash
RAM
Z8F322x with 32KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0 to 70C Z8F3221PM020SC Z8F3221AN020SC Z8F3221VN020SC Z8F3222AR020SC Z8F3222VS020SC 32KB 32KB 32KB 32KB 32KB 2KB 2KB 2KB 2KB 2KB 29 23 31 23 31 23 46 24 46 24 3 3 3 4 4 8 8 8 12 12 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package
Extended Temperature: -40 to 105C Z8F3221PM020EC Z8F3221AN020EC Z8F3221VN020EC Z8F3222AR020EC Z8F3222VS020EC 32KB 32KB 32KB 32KB 32KB 2KB 2KB 2KB 2KB 2KB 29 23 31 23 31 23 46 24 46 24 3 3 3 4 4 8 8 8 12 12 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package
Automotive/Industrial Temperature: -40 to 125C Z8F3221PM020AC Z8F3221AN020AC Z8F3221VN020AC Z8F3222AR020AC Z8F3222VS020AC 32KB 32KB 32KB 32KB 32KB 2KB 2KB 2KB 2KB 2KB 29 23 31 23 31 23 46 24 46 24 3 3 3 4 4 8 8 8 12 12 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package
Note: Replace C with G for lead-free packaging.
PS019915-1005
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Description Ordering Information
SPI
Z8 Encore!(R) 64K Series Product Specification
265
16-Bit Timers w/PWM
10-Bit A/D Channels
Part Number
UARTs with IrDA
Interrupts
I/O Lines
Flash
RAM
Z8F242x with 24KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0 to 70C Z8F2421PM020SC Z8F2421AN020SC Z8F2421VN020SC Z8F2422AR020SC Z8F2422VS020SC 24KB 24KB 24KB 24KB 24KB 2KB 2KB 2KB 2KB 2KB 29 23 31 23 31 23 46 24 46 24 3 3 3 4 4 8 8 8 12 12 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package
Extended Temperature: -40 to 105C Z8F2421PM020EC Z8F2421AN020EC Z8F2421VN020EC Z8F2422AR020EC Z8F2422VS020EC 24KB 24KB 24KB 24KB 24KB 2KB 2KB 2KB 2KB 2KB 29 23 31 23 31 23 46 24 46 24 3 3 3 4 4 8 8 8 12 12 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package
Automotive/Industrial Temperature: -40 to 125C Z8F2421PM020AC Z8F2421AN020AC Z8F2421VN020AC Z8F2422AR020AC Z8F2422VS020AC 24KB 24KB 24KB 24KB 24KB 2KB 2KB 2KB 2KB 2KB 29 23 31 23 31 23 46 24 46 24 3 3 3 4 4 8 8 8 12 12 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package
Note: Replace C with G for lead-free packaging.
PS019915-1005
I 2C
Description Ordering Information
SPI
Z8 Encore!(R) 64K Series Product Specification
266
16-Bit Timers w/PWM
10-Bit A/D Channels
Part Number
UARTs with IrDA
Interrupts
I/O Lines
Flash
RAM
Z8F162x with 16KB Flash, 10-Bit Analog-to-Digital Converter Standard Temperature: 0 to 70C Z8F1621PM020SC Z8F1621AN020SC Z8F1621VN020SC Z8F1622AR020SC Z8F1622VS020SC 16KB 16KB 16KB 16KB 16KB 2KB 2KB 2KB 2KB 2KB 29 23 31 23 31 23 46 24 46 24 3 3 3 4 4 8 8 8 12 12 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package
Extended Temperature: -40 to +105C Z8F1621PM020EC Z8F1621AN020EC Z8F1621VN020EC Z8F1622AR020EC Z8F1622VS020EC 16KB 16KB 16KB 16KB 16KB 2KB 2KB 2KB 2KB 2KB 29 23 31 23 31 23 46 24 46 24 3 3 3 4 4 8 8 8 12 12 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package
Automotive/Industrial Temperature: -40 to +125C Z8F1621PM020AC Z8F1621AN020AC Z8F1621VN020AC Z8F1622AR020AC Z8F1622VS020AC Z8F64200100KIT Note: Replace C with G for lead-free packaging. 16KB 16KB 16KB 16KB 16KB 2KB 2KB 2KB 2KB 2KB 29 23 31 23 31 23 46 24 46 24 3 3 3 4 4 8 8 8 12 12 1 1 1 1 1 1 1 1 1 1 2 PDIP 40-pin package 2 LQFP 44-pin package 2 PLCC 44-pin package 2 LQFP 64-pin package 2 PLCC 68-pin package Development Kit
For technical and customer support, hardware and software development tools, visit the ZiLOG web site at www.zilog.com. The latest released version of ZDS can be downloaded from this site.
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Description Ordering Information
SPI
Z8 Encore!(R) 64K Series Product Specification
267
Part Number Suffix Designations
Z8 F 64 21 A N 020 S C Environmental Flow: C = Plastic Standard G = Lead Free Package Temperature Range (C): S = Standard, 0 to 70 E = Extended, -40 to +105 A = Automotive/Industrial, -40 to +125 Speed: 020 = 20MHz Pin Count: M = 40 pins N = 44 pins R = 64 pins S = 68 pins T = 80 pins Package: A = LQFP F = QFP P = PDIP V = PLCC Device Type Memory Size: 64 KB Flash, 4 KB RAM 48 KB Flash, 4 KB RAM 32 KB Flash, 2 KB RAM 24 KB Flash, 2 KB RAM 16 KB Flash, 2 KB RAM Memory Type: F = Flash Device Family
Example: Part number Z8F6421AN020SC is an 8-bit microcontroller product in an LQFP package, using 44 pins, operating with a maximum 20MHz external clock frequency over a 0C to +70C temperature range and built using the Plastic-Standard environmental flow.
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Ordering Information
Z8 Encore!(R) 64K Series Product Specification
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Document Information
Document Number Description The Document Control Number that appears in the footer on each page of this document contains unique identifying attributes, as indicated in the following table:
PS 0199 07 0204 Product Specification Unique Document Number Revision Number Month and Year Published
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Z8 Encore!(R) 64K Series Product Specification
269
Customer Feedback Form
The Z8 Encore!(R) 64K Series Product Specification
If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions!
Customer Information
Name Company Address City/State/Zip Country Phone Fax E-Mail
Product Information
Part #, Serial #, Board Fab #, or Rev. # Software Version Document Number Host Computer Description/Type
Return Information ZiLOG, Inc. 532 Race Street San Jose, CA 95126 Fax: (408) 558-8536 Problem Description or Suggestion
Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary. ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________
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Index
Symbols
# 236 % 236 @ 236
additional symbols 236 address space 17 ADDX 238 analog signals 14 analog-to-digital converter (ADC) 171 AND 241 ANDX 241 arithmetic instructions 238 assembly language programming 233 assembly language syntax 234
Numerics
10-bit ADC 4 40-lead plastic dual-inline package 257 44-lead low-profile quad flat package 258 44-lead plastic lead chip carrier package 259 64-lead low-profile quad flat package 259 68-lead plastic lead chip carrier package 260 80-lead quad flat package 261
B
B 236 b 235 baud rate generator, UART 108 BCLR 239 binary number suffix 236 BIT 239 bit 235 clear 239 manipulation instructions 239 set 239 set or clear 239 swap 239 test and jump 241 test and jump if non-zero 241 test and jump if zero 241 bit jump and test if non-zero 241 bit swap 242 block diagram 3 block transfer instructions 239 BRK 241 BSET 239 BSWAP 239, 242 BTJ 241 BTJNZ 241 BTJZ 241
A
absolute maximum ratings 209 AC characteristics 224 ADC 238 architecture 171 automatic power-down 172 block diagram 172 continuous conversion 173 control register 175 control register definitions 175 data high byte register 176 data low bits register 176 DMA control 174 electrical characteristics and timing 222 operation 172 single-shot conversion 173 ADCCTL register 175 ADCDH register 176 ADCDL register 176 ADCX 238 ADD 238 add - extended addressing 238 add with carry 238 add with carry - extended addressing 238
C
CALL procedure 241 capture mode 89 capture/compare mode 89
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cc 235 CCF 240 characteristics, electrical 209 clear 240 clock phase (SPI) 128 CLR 240 COM 241 compare 89 compare - extended addressing 238 compare mode 89 compare with carry 238 compare with carry - extended addressing 238 complement 241 complement carry flag 239, 240 condition code 235 continuous conversion (ADC) 173 continuous mode 89 control register definition, UART 109 control register, I2C 155 counter modes 89 CP 238 CPC 238 CPCX 238 CPU and peripheral overview 3 CPU control instructions 240 CPX 238 customer feedback form 269 customer information 269
direct address 235 direct memory access controller 161 disable interrupts 240 DJNZ 241 DMA address high nibble register 165 configuring for DMA_ADC data transfer 163 confiigurting DMA0-1 data transfer 162 control of ADC 174 control register 163 control register definitions 163 controller 5 DMA_ADC address register 167 DMA_ADC control register 168 DMA_ADC operation 162 end address low byte register 166 I/O address register 165 operation 161 start/current address low byte register 166 status register 169 DMAA_STAT register 169 DMAACTL register 168 DMAxCTL register 164 DMAxEND register 167 DMAxH register 165 DMAxI/O address (DMAxIO) 165 DMAxIO register 165 DMAxSTART register 166 document number description 268 dst 236
D
DA 235, 238 data register, I2C 152 DC characteristics 211 debugger, on-chip 193 DEC 238 decimal adjust 238 decrement 238 decrement and jump non-zero 241 decrement word 238 DECW 238 destination operand 236 device, port availability 51 DI 240
E
EI 240 electrical characteristics 209 ADC 222 flash memory and timing 221 GPIO input data sample timing 225 watch-dog timer 221 enable interrupt 240 ER 235 extended addressing register 235 external pin reset 46 external RC oscillator 220
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Z8 Encore!(R) 64K Series Product Specification
272
eZ8 CPU features 3 eZ8 CPU instruction classes 238 eZ8 CPU instruction notation 234 eZ8 CPU instruction set 233 eZ8 CPU instruction summary 242
F
FCTL register 185 features, Z8 Encore! 1 first opcode map 255 FLAGS 236 flags register 236 flash controller 4 option bit address space 190 option bit configuration - reset 190 program memory address 0001H 192 flash memory arrangement 179 byte programming 182 code protection 181 configurations 178 control register definitions 185 controller bypass 184 electrical characteristics and timing 221 flash control register 185 flash status register 186 frequency high and low byte registers 189 mass erase 184 operation 180 operation timing 181 page erase 183 page select register 187 FPS register 187 FSTAT register 186
control register definitions 54 input data sample timing 225 interrupts 54 port A-H address registers 55 port A-H alternate function sub-registers 57 port A-H control registers 56 port A-H data direction sub-registers 57 port A-H high drive enable sub-registers 59 port A-H input data registers 60 port A-H output control sub-registers 58 port A-H output data registers 61 port A-H STOP mode recovery sub-registers 59 port availability by device 51 port input timing 225 port output timing 226
H
H 236 HALT 240 halt mode 50, 240 hexadecimal number prefix/suffix 236
I
I2C 4 10-bit address read transaction 150 10-bit address transaction 147 10-bit addressed slave data transfer format 147 10-bit receive data format 150 7-bit address transaction 145 7-bit address, reading a transaction 149 7-bit addressed slave data transfer format 144, 145, 146 7-bit receive data transfer format 149 baud high and low byte registers 156, 158, 160 C status register 153 control register definitions 152 controller 139 controller signals 13 interrupts 141 operation 140 SDA and SCL signals 141 stop and start conditions 143
G
gated mode 89 general-purpose I/O 51 GPIO 4, 51 alternate functions 52 architecture 52
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Z8 Encore!(R) 64K Series Product Specification
273
I2CBRH register 157, 158, 160 I2CBRL register 157 I2CCTL register 155 I2CDATA register 153 I2CSTAT register 153 IM 235 immediate data 235 immediate operand prefix 236 INC 238 increment 238 increment word 238 INCW 238 indexed 235 indirect address prefix 236 indirect register 235 indirect register pair 235 indirect working register 235 indirect working register pair 235 infrared encoder/decoder (IrDA) 120 instruction set, ez8 CPU 233 instructions ADC 238 ADCX 238 ADD 238 ADDX 238 AND 241 ANDX 241 arithmetic 238 BCLR 239 BIT 239 bit manipulation 239 block transfer 239 BRK 241 BSET 239 BSWAP 239, 242 BTJ 241 BTJNZ 241 BTJZ 241 CALL 241 CCF 239, 240 CLR 240 COM 241 CP 238 CPC 238
CPCX 238 CPU control 240 CPX 238 DA 238 DEC 238 DECW 238 DI 240 DJNZ 241 EI 240 HALT 240 INC 238 INCW 238 IRET 241 JP 241 LD 240 LDC 240 LDCI 239, 240 LDE 240 LDEI 239 LDX 240 LEA 240 load 240 logical 241 MULT 238 NOP 240 OR 241 ORX 241 POP 240 POPX 240 program control 241 PUSH 240 PUSHX 240 RCF 239, 240 RET 241 RL 242 RLC 242 rotate and shift 242 RR 242 RRC 242 SBC 239 SCF 239, 240 SRA 242 SRL 242 SRP 240
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STOP 240 SUB 239 SUBX 239 SWAP 242 TCM 239 TCMX 239 TM 239 TMX 239 TRAP 241 watch-dog timer refresh 240 XOR 241 XORX 241 instructions, eZ8 classes of 238 interrupt control register 74 interrupt controller 5, 62 architecture 62 interrupt assertion types 65 interrupt vectors and priority 65 operation 64 register definitions 66 software interrupt assertion 65 interrupt edge select register 72 interrupt port select register 73 interrupt request 0 register 66 interrupt request 1 register 67 interrupt request 2 register 68 interrupt return 241 interrupt vector listing 62 interrupts not acknowledge 141 receive 141 SPI 131 transmit 141 UART 106 introduction 1 IR 235 Ir 235 IrDA architecture 120 block diagram 120 control register definitions 124 operation 121 receiving data 122 transmitting data 121
IRET 241 IRQ0 enable high and low bit registers 69 IRQ1 enable high and low bit registers 70 IRQ2 enable high and low bit registers 71 IRR 235 Irr 235
J
JP 241 jump, conditional, relative, and relative conditional 241
L
LD 240 LDC 240 LDCI 239, 240 LDE 240 LDEI 239, 240 LDX 240 LEA 240 load 240 load constant 239 load constant to/from program memory 240 load constant with auto-increment addresses 240 load effective address 240 load external data 240 load external data to/from data memory and autoincrement addresses 239 load external to/from data memory and auto-increment addresses 240 load instructions 240 load using extended addressing 240 logical AND 241 logical AND/extended addressing 241 logical exclusive OR 241 logical exclusive OR/extended addressing 241 logical instructions 241 logical OR 241 logical OR/extended addressing 241 low power modes 49 LQFP 44 lead 258
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64 lead 259
X 235 notational shorthand 235
M
master interrupt enable 64 master-in, slave-out and-in 127 memory program 18 MISO 127 mode capture 89 capture/compare 89 continuous 89 counter 89 gated 89 one-shot 89 PWM 89 modes 89 MOSI 127 MULT 238 multiply 238 multiprocessor mode, UART 104
O
OCD architecture 193 auto-baud detector/generator 196 baud rate limits 196 block diagram 193 breakpoints 197 commands 198 control register 202 data format 196 DBG pin to RS-232 Interface 194 debug mode 195 debugger break 241 interface 194 serial errors 197 status register 204 timing 227 OCD commands execute instruction (12H) 202 read data memory (0DH) 201 read OCD control register (05H) 200 read OCD revision (00H) 199 read OCD status register (02H) 199 read program counter (07H) 200 read program memory (0BH) 201 read program memory CRC (0EH) 201 read register (09H) 200 step instruction (10H) 202 stuff instruction (11H) 202 write data memory (0CH) 201 write OCD control register (04H) 199 write program counter (06H) 200 write program memory (0AH) 200 write register (08H) 200 on-chip debugger 5 on-chip debugger (OCD) 193 on-chip debugger signals 15 on-chip oscillator 205 one-shot mode 89 opcode map
N
NOP (no operation) 240 not acknowledge interrupt 141 notation b 235 cc 235 DA 235 ER 235 IM 235 IR 235 Ir 235 IRR 235 Irr 235 p 235 R 235 r 235 RA 235 RR 235 rr 235 vector 235
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abbreviations 254 cell description 253 first 255 second after 1FH 256 Operational Description 98 OR 241 ordering information 262 ORX 241 oscillator signals 14
problem description or suggestion 269 product information 269 program control instructions 241 program counter 236 program memory 18 PUSH 240 push using extended addressing 240 PUSHX 240 PWM mode 89 PxADDR register 55 PxCTL register 56
P
p 235 packaging LQFP
Q
QFP 261
44 lead 258 64 lead 259
PDIP 257 PLCC
R
R 235 r 235 RA register address 235 RCF 239, 240 receive 10-bit data format (I2C) 150 7-bit data transfer format (I2C) 149 IrDA data 122 receive interrupt 141 receiving UART data-interrupt-driven method 103 receiving UART data-polled method 102 register 136, 165, 235 ADC control (ADCCTL) 175 ADC data high byte (ADCDH) 176 ADC data low bits (ADCDL) 176 baud low and high byte (I2C) 156, 158, 160 baud rate high and low byte (SPI) 138 control (SPI) 133 control, I2C 155 data, SPI 133 DMA status (DMAA_STAT) 169 DMA_ADC address 167 DMA_ADC control DMAACTL) 168 DMAx address high nibble (DMAxH) 165 DMAx control (DMAxCTL) 164
44 lead 259 68 lead 260
QFP 261 part number description 267 part selection guide 2 PC 236 PDIP 257 peripheral AC and DC electrical characteristics 219 PHASE=0 timing (SPI) 129 PHASE=1 timing (SPI) 130 pin characteristics 16 PLCC 44 lead 259 68-lead 260 polarity 235 POP 240 pop using extended addressing 240 POPX 240 port availability, device 51 port input timing (GPIO) 225 port output timing, GPIO 226 power supply signals 15 power-down, automatic (ADC) 172 power-on and voltage brown-out 219 power-on reset (POR) 44
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DMAx end/address low byte (DMAxEND) 167 DMAx start/current address low byte register (DMAxSTART) 166 flash control (FCTL) 185 flash high and low byte (FFREQH and FREEQL) 189 flash page select (FPS) 187 flash status (FSTAT) 186 GPIO port A-H address (PxADDR) 55 GPIO port A-H alternate function sub-registers 57 GPIO port A-H control address (PxCTL) 56 GPIO port A-H data direction sub-registers 57 I2C baud rate high (I2CBRH) 157, 158, 160 I2C control (I2CCTL) 155 I2C data (I2CDATA) 153 I2C status 153 I2C status (I2CSTAT) 153 I2Cbaud rate low (I2CBRL) 157 mode, SPI 136 OCD control 202 OCD status 204 SPI baud rate high byte (SPIBRH) 138 SPI baud rate low byte (SPIBRL) 138 SPI control (SPICTL) 134 SPI data (SPIDATA) 133 SPI status (SPISTAT) 135 status, I2C 153 status, SPI 135 UARTx baud rate high byte (UxBRH) 116 UARTx baud rate low byte (UxBRL) 116 UARTx Control 0 (UxCTL0) 112, 115 UARTx control 1 (UxCTL1) 113 UARTx receive data (UxRXD) 110 UARTx status 0 (UxSTAT0) 110 UARTx status 1 (UxSTAT1) 112 UARTx transmit data (UxTXD) 109 watch-dog timer control (WDTCTL) 94 watch-dog timer reload high byte (WDTH) 96 watch-dog timer reload low byte (WDTL) 97 watch-dog timer reload upper byte (WDTU) 96 register file 17 register file address map 21 register pair 235
register pointer 236 reset and STOP mode characteristics 43 and STOP mode recovery 43 carry flag 239 controller 5 sources 44 RET 241 return 241 return information 269 RL 242 RLC 242 rotate and shift instructions 242 rotate left 242 rotate left through carry 242 rotate right 242 rotate right through carry 242 RP 236 RR 235, 242 rr 235 RRC 242
S
SBC 239 SCF 239, 240 SCK 127 SDA and SCL (IrDA) signals 141 second opcode map after 1FH 256 serial clock 127 serial peripheral interface (SPI) 125 set carry flag 239, 240 set register pointer 240 shift right arithmetic 242 shift right logical 242 signal descriptions 13 single-shot conversion (ADC) 173 SIO 5 slave data transfer formats (I2C) 147 slave select 128 software trap 241 source operand 236 SP 236 SPI
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architecture 125 baud rate generator 132 baud rate high and low byte register 138 clock phase 128 configured as slave 126 control register 133 control register definitions 133 data register 133 error detection 131 interrupts 131 mode fault error 131 mode register 136 multi-master operation 130 operation 126 overrun error 131 signals 127 single master, multiple slave system 126 single master, single slave system 125 status register 135 timing, PHASE = 0 129 timing, PHASE=1 130 SPI controller signals 13 SPI mode (SPIMODE) 136 SPIBRH register 138 SPIBRL register 138 SPICTL register 134 SPIDATA register 133 SPIMODE register 136 SPISTAT register 135 SRA 242 src 236 SRL 242 SRP 240 SS, SPI signal 127 stack pointer 236 status register, I2C 153 STOP 240 STOP mode 49, 240 STOP mode recovery sources 47 using a GPIO port pin transition 48 using watch-dog timer time-out 48 SUB 239 subtract 239
subtract - extended addressing 239 subtract with carry 239 subtract with carry - extended addressing 239 SUBX 239 SWAP 242 swap nibbles 242 symbols, additional 236 system and core resets 44
T
TCM 239 TCMX 239 test complement under mask 239 test complement under mask - extended addressing 239 test under mask 239 test under mask - extended addressing 239 timer signals 14 timers 5, 75 architecture 75 block diagram 76 capture mode 80, 89 capture/compare mode 83, 89 compare mode 81, 89 continuous mode 77, 89 counter mode 78 counter modes 89 gated mode 82, 89 one-shot mode 76, 89 operating mode 76 PWM mode 79, 89 reading the timer count values 84 reload high and low byte registers 85 timer control register definitions 84 timer output signal operation 84 timers 0-3 control 0 registers 88 control 1 registers 88 high and low byte registers 84, 87 TM 239 TMX 239 transmit IrDA data 121
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transmit interrupt 141 transmitting UART data-interrupt-driven method 101 transmitting UART data-polled method 100 TRAP 241
W
watch-dog timer approximate time-out delay 92 approximate time-out delays 91 CNTL 46 control register 94 electrical characteristics and timing 221 interrupt in normal operation 92 interrupt in STOP mode 92 operation 91 refresh 92, 240 reload unlock sequence 93 reload upper, high and low registers 95 reset 46 reset in normal operation 93 reset in STOP mode 93 time-out response 92 WDTCTL register 94 WDTH register 96 WDTL register 97 working register 235 working register pair 235 WTDU register 96
U
UART 4 architecture 98 asynchronous data format without/with parity 100 baud rate generator 108 baud rates table 117 control register definitions 109 controller signals 14 data format 99 interrupts 106 multiprocessor mode 104 receiving data using interrupt-driven method 103 receiving data using the polled method 102 transmitting data using the interrupt-driven method 101 transmitting data using the polled method 100 x baud rate high and low registers 115 x control 0 and control 1 registers 112 x status 0 and status 1 registers 110, 112 UxBRH register 116 UxBRL register 116 UxCTL0 register 112, 115 UxCTL1 register 113 UxRXD register 110 UxSTAT0 register 110 UxSTAT1 register 112 UxTXD register 109
X
X 235 XOR 241 XORX 241
Z
Z8 Encore! block diagram 3 features 1 introduction 1 part selection guide 2
V
vector 235 voltage brown-out reset (VBR) 45
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